mchange100.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mchange100 is
port(clk:in std_logic;                -------时钟信号
     clr:in std_logic;                -------清零信号
     ld:in std_logic;                 ------置数端
     m:in integer range 0 to 99;      --------模值输入端
     q:buffer integer range 0 to 99); ------计数器输出
end;
architecture one of mchange100 is
signal md:integer range 0 to 99;
begin
process(clk,clr,m)
begin
md<=m-1;
if clr='1' then  q<=0;
elsif clk'event and clk='1' then 
    if ld='1' then  q<=md;  
	else if q=md then q<=0;
	     else q<=q+1;
	     end if;
	end if;
end if;
end process;
end;