fifo.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register a\[2\] register dout\[6\]~reg0 174.95 MHz 5.716 ns Internal " "Info: Clock \"clk\" has Internal fmax of 174.95 MHz between source register \"a\[2\]\" and destination register \"dout\[6\]~reg0\" (period= 5.716 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.483 ns + Longest register register " "Info: + Longest register to register delay is 5.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[2\] 1 REG LCFF_X18_Y5_N13 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y5_N13; Fanout = 10; REG Node = 'a\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.647 ns) 1.817 ns Equal1~81 2 COMB LCCOMB_X18_Y5_N26 1 " "Info: 2: + IC(1.170 ns) + CELL(0.647 ns) = 1.817 ns; Loc. = LCCOMB_X18_Y5_N26; Fanout = 1; COMB Node = 'Equal1~81'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.817 ns" { a[2] Equal1~81 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.388 ns) + CELL(0.624 ns) 2.829 ns y~351 3 COMB LCCOMB_X18_Y5_N6 4 " "Info: 3: + IC(0.388 ns) + CELL(0.624 ns) = 2.829 ns; Loc. = LCCOMB_X18_Y5_N6; Fanout = 4; COMB Node = 'y~351'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.012 ns" { Equal1~81 y~351 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.206 ns) 3.417 ns process0~4 4 COMB LCCOMB_X18_Y5_N30 9 " "Info: 4: + IC(0.382 ns) + CELL(0.206 ns) = 3.417 ns; Loc. = LCCOMB_X18_Y5_N30; Fanout = 9; COMB Node = 'process0~4'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.588 ns" { y~351 process0~4 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.206 ns) 4.033 ns dout\[0\]~1730 5 COMB LCCOMB_X18_Y5_N14 8 " "Info: 5: + IC(0.410 ns) + CELL(0.206 ns) = 4.033 ns; Loc. = LCCOMB_X18_Y5_N14; Fanout = 8; COMB Node = 'dout\[0\]~1730'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.616 ns" { process0~4 dout[0]~1730 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.855 ns) 5.483 ns dout\[6\]~reg0 6 REG LCFF_X17_Y5_N21 1 " "Info: 6: + IC(0.595 ns) + CELL(0.855 ns) = 5.483 ns; Loc. = LCFF_X17_Y5_N21; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.450 ns" { dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.538 ns ( 46.29 % ) " "Info: Total cell delay = 2.538 ns ( 46.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.945 ns ( 53.71 % ) " "Info: Total interconnect delay = 2.945 ns ( 53.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.483 ns" { a[2] Equal1~81 y~351 process0~4 dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.483 ns" { a[2] Equal1~81 y~351 process0~4 dout[0]~1730 dout[6]~reg0 } { 0.000ns 1.170ns 0.388ns 0.382ns 0.410ns 0.595ns } { 0.000ns 0.647ns 0.624ns 0.206ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.031 ns - Smallest " "Info: - Smallest clock skew is 0.031 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.824 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 82 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.824 ns dout\[6\]~reg0 3 REG LCFF_X17_Y5_N21 1 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.824 ns; Loc. = LCFF_X17_Y5_N21; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.18 % ) " "Info: Total cell delay = 1.756 ns ( 62.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.82 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 82 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.793 ns a\[2\] 3 REG LCFF_X18_Y5_N13 10 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X18_Y5_N13; Fanout = 10; REG Node = 'a\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl a[2] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl a[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl a[2] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl a[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl a[2] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.483 ns" { a[2] Equal1~81 y~351 process0~4 dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.483 ns" { a[2] Equal1~81 y~351 process0~4 dout[0]~1730 dout[6]~reg0 } { 0.000ns 1.170ns 0.388ns 0.382ns 0.410ns 0.595ns } { 0.000ns 0.647ns 0.624ns 0.206ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl a[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl a[2] } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dout\[6\]~reg0 rd clk 9.003 ns register " "Info: tsu for register \"dout\[6\]~reg0\" (data pin = \"rd\", clock pin = \"clk\") is 9.003 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.867 ns + Longest pin register " "Info: + Longest pin to register delay is 11.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns rd 1 PIN PIN_60 6 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_60; Fanout = 6; PIN Node = 'rd'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.586 ns) + CELL(0.544 ns) 8.074 ns process0~138 2 COMB LCCOMB_X17_Y5_N14 7 " "Info: 2: + IC(6.586 ns) + CELL(0.544 ns) = 8.074 ns; Loc. = LCCOMB_X17_Y5_N14; Fanout = 7; COMB Node = 'process0~138'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.130 ns" { rd process0~138 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.624 ns) 9.801 ns process0~4 3 COMB LCCOMB_X18_Y5_N30 9 " "Info: 3: + IC(1.103 ns) + CELL(0.624 ns) = 9.801 ns; Loc. = LCCOMB_X18_Y5_N30; Fanout = 9; COMB Node = 'process0~4'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.727 ns" { process0~138 process0~4 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.206 ns) 10.417 ns dout\[0\]~1730 4 COMB LCCOMB_X18_Y5_N14 8 " "Info: 4: + IC(0.410 ns) + CELL(0.206 ns) = 10.417 ns; Loc. = LCCOMB_X18_Y5_N14; Fanout = 8; COMB Node = 'dout\[0\]~1730'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.616 ns" { process0~4 dout[0]~1730 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.855 ns) 11.867 ns dout\[6\]~reg0 5 REG LCFF_X17_Y5_N21 1 " "Info: 5: + IC(0.595 ns) + CELL(0.855 ns) = 11.867 ns; Loc. = LCFF_X17_Y5_N21; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.450 ns" { dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.173 ns ( 26.74 % ) " "Info: Total cell delay = 3.173 ns ( 26.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.694 ns ( 73.26 % ) " "Info: Total interconnect delay = 8.694 ns ( 73.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.867 ns" { rd process0~138 process0~4 dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.867 ns" { rd rd~combout process0~138 process0~4 dout[0]~1730 dout[6]~reg0 } { 0.000ns 0.000ns 6.586ns 1.103ns 0.410ns 0.595ns } { 0.000ns 0.944ns 0.544ns 0.624ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.824 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 82 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.824 ns dout\[6\]~reg0 3 REG LCFF_X17_Y5_N21 1 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.824 ns; Loc. = LCFF_X17_Y5_N21; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.18 % ) " "Info: Total cell delay = 1.756 ns ( 62.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.82 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.867 ns" { rd process0~138 process0~4 dout[0]~1730 dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.867 ns" { rd rd~combout process0~138 process0~4 dout[0]~1730 dout[6]~reg0 } { 0.000ns 0.000ns 6.586ns 1.103ns 0.410ns 0.595ns } { 0.000ns 0.944ns 0.544ns 0.624ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.824 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] dout\[3\]~reg0 8.983 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through register \"dout\[3\]~reg0\" is 8.983 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 82 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.793 ns dout\[3\]~reg0 3 REG LCFF_X18_Y5_N25 1 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X18_Y5_N25; Fanout = 1; REG Node = 'dout\[3\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl dout[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.886 ns + Longest register pin " "Info: + Longest register to pin delay is 5.886 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[3\]~reg0 1 REG LCFF_X18_Y5_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y5_N25; Fanout = 1; REG Node = 'dout\[3\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[3]~reg0 } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.670 ns) + CELL(3.216 ns) 5.886 ns dout\[3\] 2 PIN PIN_129 0 " "Info: 2: + IC(2.670 ns) + CELL(3.216 ns) = 5.886 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.886 ns" { dout[3]~reg0 dout[3] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.216 ns ( 54.64 % ) " "Info: Total cell delay = 3.216 ns ( 54.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.670 ns ( 45.36 % ) " "Info: Total interconnect delay = 2.670 ns ( 45.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.886 ns" { dout[3]~reg0 dout[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.886 ns" { dout[3]~reg0 dout[3] } { 0.000ns 2.670ns } { 0.000ns 3.216ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl dout[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.886 ns" { dout[3]~reg0 dout[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.886 ns" { dout[3]~reg0 dout[3] } { 0.000ns 2.670ns } { 0.000ns 3.216ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "data\[2\]\[5\] din\[5\] clk 0.099 ns register " "Info: th for register \"data\[2\]\[5\]\" (data pin = \"din\[5\]\", clock pin = \"clk\") is 0.099 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 82 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 2.800 ns data\[2\]\[5\] 3 REG LCFF_X22_Y6_N27 1 " "Info: 3: + IC(0.905 ns) + CELL(0.666 ns) = 2.800 ns; Loc. = LCFF_X22_Y6_N27; Fanout = 1; REG Node = 'data\[2\]\[5\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { clk~clkctrl data[2][5] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.71 % ) " "Info: Total cell delay = 1.756 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.044 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.044 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { clk clk~clkctrl data[2][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { clk clk~combout clk~clkctrl data[2][5] } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.007 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns din\[5\] 1 PIN PIN_90 8 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 8; PIN Node = 'din\[5\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[5] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.593 ns) + CELL(0.206 ns) 2.899 ns data\[2\]\[5\]~feeder 2 COMB LCCOMB_X22_Y6_N26 1 " "Info: 2: + IC(1.593 ns) + CELL(0.206 ns) = 2.899 ns; Loc. = LCCOMB_X22_Y6_N26; Fanout = 1; COMB Node = 'data\[2\]\[5\]~feeder'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.799 ns" { din[5] data[2][5]~feeder } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.007 ns data\[2\]\[5\] 3 REG LCFF_X22_Y6_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.007 ns; Loc. = LCFF_X22_Y6_N27; Fanout = 1; REG Node = 'data\[2\]\[5\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { data[2][5]~feeder data[2][5] } "NODE_NAME" } } { "fifo.vhd" "" { Text "D:/my_eda/FIFO/fifo.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.414 ns ( 47.02 % ) " "Info: Total cell delay = 1.414 ns ( 47.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.593 ns ( 52.98 % ) " "Info: Total interconnect delay = 1.593 ns ( 52.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.007 ns" { din[5] data[2][5]~feeder data[2][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.007 ns" { din[5] din[5]~combout data[2][5]~feeder data[2][5] } { 0.000ns 0.000ns 1.593ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { clk clk~clkctrl data[2][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.800 ns" { clk clk~combout clk~clkctrl data[2][5] } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.007 ns" { din[5] data[2][5]~feeder data[2][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.007 ns" { din[5] din[5]~combout data[2][5]~feeder data[2][5] } { 0.000ns 0.000ns 1.593ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}