pll.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 25 20:18:44 2007 " "Info: Processing started: Wed Apr 25 20:18:44 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off pll -c pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pll -c pll --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"altpll:altpll_component\|_clk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"altpll:altpll_component\|_clk1\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "altpll:altpll_component\|_clk2 " "Info: No valid register-to-register data paths exist for clock \"altpll:altpll_component\|_clk2\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "inclk0 " "Info: No valid register-to-register data paths exist for clock \"inclk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk0 c1 altpll:altpll_component\|_clk1 3.199 ns clock " "Info: tco from clock \"inclk0\" to destination pin \"c1\" through clock \"altpll:altpll_component\|_clk1\" is 3.199 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "inclk0 altpll:altpll_component\|_clk1 -2.438 ns + " "Info: + Offset between input clock \"inclk0\" and output clock \"altpll:altpll_component\|_clk1\" is -2.438 ns" {  } { { "pll.vhd" "" { Text "D:/my_eda2/lpm_pll/pll.vhd" 46 -1 0 } } { "altpll.tdf" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.637 ns + Longest clock pin " "Info: + Longest clock to pin delay is 5.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll:altpll_component\|_clk1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'altpll:altpll_component\|_clk1~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { altpll:altpll_component|_clk1 altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.485 ns) + CELL(3.236 ns) 5.637 ns c1 3 PIN PIN_135 0 " "Info: 3: + IC(1.485 ns) + CELL(3.236 ns) = 5.637 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'c1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.721 ns" { altpll:altpll_component|_clk1~clkctrl c1 } "NODE_NAME" } } { "pll.vhd" "" { Text "D:/my_eda2/lpm_pll/pll.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 57.41 % ) " "Info: Total cell delay = 3.236 ns ( 57.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.401 ns ( 42.59 % ) " "Info: Total interconnect delay = 2.401 ns ( 42.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.637 ns" { altpll:altpll_component|_clk1 altpll:altpll_component|_clk1~clkctrl c1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.637 ns" { altpll:altpll_component|_clk1 altpll:altpll_component|_clk1~clkctrl c1 } { 0.000ns 0.916ns 1.485ns } { 0.000ns 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.637 ns" { altpll:altpll_component|_clk1 altpll:altpll_component|_clk1~clkctrl c1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.637 ns" { altpll:altpll_component|_clk1 altpll:altpll_component|_clk1~clkctrl c1 } { 0.000ns 0.916ns 1.485ns } { 0.000ns 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 25 20:18:46 2007 " "Info: Processing ended: Wed Apr 25 20:18:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}