📄 elevator.tan.qmsg

📁 基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register k55 register en_up 152.77 MHz 6.546 ns Internal " "Info: Clock \"clk\" has Internal fmax of 152.77 MHz between source register \"k55\" and destination register \"en_up\" (period= 6.546 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.282 ns + Longest register register " "Info: + Longest register to register delay is 6.282 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns k55 1 REG LCFF_X17_Y11_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y11_N15; Fanout = 4; REG Node = 'k55'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { k55 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.370 ns) 0.817 ns en_down~1621 2 COMB LCCOMB_X17_Y11_N12 4 " "Info: 2: + IC(0.447 ns) + CELL(0.370 ns) = 0.817 ns; Loc. = LCCOMB_X17_Y11_N12; Fanout = 4; COMB Node = 'en_down~1621'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { k55 en_down~1621 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.206 ns) 1.406 ns opendoor~2131 3 COMB LCCOMB_X17_Y11_N18 4 " "Info: 3: + IC(0.383 ns) + CELL(0.206 ns) = 1.406 ns; Loc. = LCCOMB_X17_Y11_N18; Fanout = 4; COMB Node = 'opendoor~2131'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.589 ns" { en_down~1621 opendoor~2131 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.165 ns) + CELL(0.589 ns) 4.160 ns en_up~1978 4 COMB LCCOMB_X17_Y12_N0 1 " "Info: 4: + IC(2.165 ns) + CELL(0.589 ns) = 4.160 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 1; COMB Node = 'en_up~1978'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { opendoor~2131 en_up~1978 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.111 ns) + CELL(0.206 ns) 5.477 ns en_up~1979 5 COMB LCCOMB_X17_Y11_N20 1 " "Info: 5: + IC(1.111 ns) + CELL(0.206 ns) = 5.477 ns; Loc. = LCCOMB_X17_Y11_N20; Fanout = 1; COMB Node = 'en_up~1979'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.317 ns" { en_up~1978 en_up~1979 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.319 ns) 6.174 ns en_up~1983 6 COMB LCCOMB_X17_Y11_N2 1 " "Info: 6: + IC(0.378 ns) + CELL(0.319 ns) = 6.174 ns; Loc. = LCCOMB_X17_Y11_N2; Fanout = 1; COMB Node = 'en_up~1983'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.697 ns" { en_up~1979 en_up~1983 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.282 ns en_up 7 REG LCFF_X17_Y11_N3 7 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 6.282 ns; Loc. = LCFF_X17_Y11_N3; Fanout = 7; REG Node = 'en_up'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { en_up~1983 en_up } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.798 ns ( 28.62 % ) " "Info: Total cell delay = 1.798 ns ( 28.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.484 ns ( 71.38 % ) " "Info: Total interconnect delay = 4.484 ns ( 71.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.282 ns" { k55 en_down~1621 opendoor~2131 en_up~1978 en_up~1979 en_up~1983 en_up } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.282 ns" { k55 en_down~1621 opendoor~2131 en_up~1978 en_up~1979 en_up~1983 en_up } { 0.000ns 0.447ns 0.383ns 2.165ns 1.111ns 0.378ns 0.000ns } { 0.000ns 0.370ns 0.206ns 0.589ns 0.206ns 0.319ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.793 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.793 ns en_up 3 REG LCFF_X17_Y11_N3 7 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y11_N3; Fanout = 7; REG Node = 'en_up'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl en_up } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl en_up } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl en_up } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.793 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.793 ns k55 3 REG LCFF_X17_Y11_N15 4 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y11_N15; Fanout = 4; REG Node = 'k55'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl k55 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl k55 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl en_up } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl en_up } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl k55 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.282 ns" { k55 en_down~1621 opendoor~2131 en_up~1978 en_up~1979 en_up~1983 en_up } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.282 ns" { k55 en_down~1621 opendoor~2131 en_up~1978 en_up~1979 en_up~1983 en_up } { 0.000ns 0.447ns 0.383ns 2.165ns 1.111ns 0.378ns 0.000ns } { 0.000ns 0.370ns 0.206ns 0.589ns 0.206ns 0.319ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl en_up } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl en_up } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl k55 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "k55 k3 clk 10.015 ns register " "Info: tsu for register \"k55\" (data pin = \"k3\", clock pin = \"clk\") is 10.015 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.848 ns + Longest pin register " "Info: + Longest pin to register delay is 12.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns k3 1 PIN PIN_51 3 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 3; PIN Node = 'k3'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { k3 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.204 ns) + CELL(0.370 ns) 8.518 ns k66~106 2 COMB LCCOMB_X18_Y11_N20 2 " "Info: 2: + IC(7.204 ns) + CELL(0.370 ns) = 8.518 ns; Loc. = LCCOMB_X18_Y11_N20; Fanout = 2; COMB Node = 'k66~106'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.574 ns" { k3 k66~106 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.206 ns) 10.234 ns k55~252 3 COMB LCCOMB_X16_Y7_N6 1 " "Info: 3: + IC(1.510 ns) + CELL(0.206 ns) = 10.234 ns; Loc. = LCCOMB_X16_Y7_N6; Fanout = 1; COMB Node = 'k55~252'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.716 ns" { k66~106 k55~252 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.882 ns) + CELL(0.624 ns) 12.740 ns k55~253 4 COMB LCCOMB_X17_Y11_N14 1 " "Info: 4: + IC(1.882 ns) + CELL(0.624 ns) = 12.740 ns; Loc. = LCCOMB_X17_Y11_N14; Fanout = 1; COMB Node = 'k55~253'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.506 ns" { k55~252 k55~253 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 12.848 ns k55 5 REG LCFF_X17_Y11_N15 4 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 12.848 ns; Loc. = LCFF_X17_Y11_N15; Fanout = 4; REG Node = 'k55'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { k55~253 k55 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.252 ns ( 17.53 % ) " "Info: Total cell delay = 2.252 ns ( 17.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.596 ns ( 82.47 % ) " "Info: Total interconnect delay = 10.596 ns ( 82.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "12.848 ns" { k3 k66~106 k55~252 k55~253 k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "12.848 ns" { k3 k3~combout k66~106 k55~252 k55~253 k55 } { 0.000ns 0.000ns 7.204ns 1.510ns 1.882ns 0.000ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.793 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.793 ns k55 3 REG LCFF_X17_Y11_N15 4 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y11_N15; Fanout = 4; REG Node = 'k55'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl k55 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.87 % ) " "Info: Total cell delay = 1.756 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 37.13 % ) " "Info: Total interconnect delay = 1.037 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl k55 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "12.848 ns" { k3 k66~106 k55~252 k55~253 k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "12.848 ns" { k3 k3~combout k66~106 k55~252 k55~253 k55 } { 0.000ns 0.000ns 7.204ns 1.510ns 1.882ns 0.000ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.624ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { clk clk~clkctrl k55 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { clk clk~combout clk~clkctrl k55 } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[1\] led\[1\]~reg0 9.278 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[1\]\" through register \"led\[1\]~reg0\" is 9.278 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.801 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns led\[1\]~reg0 3 REG LCFF_X16_Y12_N7 2 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X16_Y12_N7; Fanout = 2; REG Node = 'led\[1\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl led[1]~reg0 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl led[1]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl led[1]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.173 ns + Longest register pin " "Info: + Longest register to pin delay is 6.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led\[1\]~reg0 1 REG LCFF_X16_Y12_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y12_N7; Fanout = 2; REG Node = 'led\[1\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { led[1]~reg0 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.937 ns) + CELL(3.236 ns) 6.173 ns led\[1\] 2 PIN PIN_45 0 " "Info: 2: + IC(2.937 ns) + CELL(3.236 ns) = 6.173 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'led\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 52.42 % ) " "Info: Total cell delay = 3.236 ns ( 52.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.937 ns ( 47.58 % ) " "Info: Total interconnect delay = 2.937 ns ( 47.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { led[1]~reg0 led[1] } { 0.000ns 2.937ns } { 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl led[1]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl led[1]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { led[1]~reg0 led[1] } { 0.000ns 2.937ns } { 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "alarm~reg0 clr clk 0.072 ns register " "Info: th for register \"alarm~reg0\" (data pin = \"clr\", clock pin = \"clk\") is 0.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.780 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.885 ns) + CELL(0.666 ns) 2.780 ns alarm~reg0 3 REG LCFF_X19_Y12_N21 1 " "Info: 3: + IC(0.885 ns) + CELL(0.666 ns) = 2.780 ns; Loc. = LCFF_X19_Y12_N21; Fanout = 1; REG Node = 'alarm~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { clk~clkctrl alarm~reg0 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.17 % ) " "Info: Total cell delay = 1.756 ns ( 63.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 36.83 % ) " "Info: Total interconnect delay = 1.024 ns ( 36.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.780 ns" { clk clk~clkctrl alarm~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.780 ns" { clk clk~combout clk~clkctrl alarm~reg0 } { 0.000ns 0.000ns 0.139ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.014 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clr 1 PIN PIN_91 13 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 13; PIN Node = 'clr'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(0.202 ns) 2.906 ns alarm~11 2 COMB LCCOMB_X19_Y12_N20 1 " "Info: 2: + IC(1.604 ns) + CELL(0.202 ns) = 2.906 ns; Loc. = LCCOMB_X19_Y12_N20; Fanout = 1; COMB Node = 'alarm~11'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.806 ns" { clr alarm~11 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.014 ns alarm~reg0 3 REG LCFF_X19_Y12_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.014 ns; Loc. = LCFF_X19_Y12_N21; Fanout = 1; REG Node = 'alarm~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { alarm~11 alarm~reg0 } "NODE_NAME" } } { "elevator.vhd" "" { Text "D:/my_eda2/elevator/elevator.vhd" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.410 ns ( 46.78 % ) " "Info: Total cell delay = 1.410 ns ( 46.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.604 ns ( 53.22 % ) " "Info: Total interconnect delay = 1.604 ns ( 53.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.014 ns" { clr alarm~11 alarm~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.014 ns" { clr clr~combout alarm~11 alarm~reg0 } { 0.000ns 0.000ns 1.604ns 0.000ns } { 0.000ns 1.100ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.780 ns" { clk clk~clkctrl alarm~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.780 ns" { clk clk~combout clk~clkctrl alarm~reg0 } { 0.000ns 0.000ns 0.139ns 0.885ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.014 ns" { clr alarm~11 alarm~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.014 ns" { clr clr~combout alarm~11 alarm~reg0 } { 0.000ns 0.000ns 1.604ns 0.000ns } { 0.000ns 1.100ns 0.202ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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