mult.fit.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Fitter Status : Successful - Wed Apr 25 15:12:54 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : mult
Top-level Entity Name : mult
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 0 / 10,570 ( 0 % )
Total pins : 33 / 336 ( 10 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 1 / 48 ( 2 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )