mult.tan.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.440 ns
From           : dataa[1]
To             : lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.788 ns
From           : lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT7
To             : result[4]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.869 ns
From           : datab[0]
To             : lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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