mult.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_TSU_RESULT" "lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1 dataa\[1\] clock 2.440 ns register " "Info: tsu for register \"lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1\" (data pin = \"dataa\[1\]\", clock pin = \"clock\") is 2.440 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.858 ns + Longest pin register " "Info: + Longest pin to register delay is 5.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns dataa\[1\] 1 PIN PIN_V16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V16; Fanout = 1; PIN Node = 'dataa\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataa[1] } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.380 ns) + CELL(0.391 ns) 5.858 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1 2 REG DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(4.380 ns) + CELL(0.391 ns) = 5.858 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.771 ns" { dataa[1] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.478 ns ( 25.23 % ) " "Info: Total cell delay = 1.478 ns ( 25.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 74.77 % ) " "Info: Total interconnect delay = 4.380 ns ( 74.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.858 ns" { dataa[1] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.858 ns" { dataa[1] dataa[1]~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } { 0.000ns 0.000ns 4.380ns } { 0.000ns 1.087ns 0.391ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.000 ns + " "Info: + Micro setup delay of destination is 0.000 ns" {  } { { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.418 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clock 1 CLK PIN_Y15 18 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.972 ns) 3.418 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1 2 REG DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(1.359 ns) + CELL(0.972 ns) = 3.418 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAA_REGOUT1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.059 ns ( 60.24 % ) " "Info: Total cell delay = 2.059 ns ( 60.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.359 ns ( 39.76 % ) " "Info: Total interconnect delay = 1.359 ns ( 39.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.418 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.418 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.972ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.858 ns" { dataa[1] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.858 ns" { dataa[1] dataa[1]~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } { 0.000ns 0.000ns 4.380ns } { 0.000ns 1.087ns 0.391ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.418 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.418 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.972ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock result\[4\] lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 11.788 ns register " "Info: tco from clock \"clock\" to destination pin \"result\[4\]\" through register \"lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0\" is 11.788 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.414 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clock 1 CLK PIN_Y15 18 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.968 ns) 3.414 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 2 REG DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(1.359 ns) + CELL(0.968 ns) = 3.414 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.327 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.055 ns ( 60.19 % ) " "Info: Total cell delay = 2.055 ns ( 60.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.359 ns ( 39.81 % ) " "Info: Total interconnect delay = 1.359 ns ( 39.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.414 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.414 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.968ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.142 ns + " "Info: + Micro clock to output delay of source is 0.142 ns" {  } { { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.232 ns + Longest register pin " "Info: + Longest register to pin delay is 8.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 1 REG DSPMULT_X10_Y7_N0 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.757 ns) 2.757 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~DATAOUT15 2 COMB DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(0.000 ns) + CELL(2.757 ns) = 2.757 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; COMB Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~DATAOUT15'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.757 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 3.635 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|result\[4\] 3 COMB DSPOUT_X11_Y1_N0 1 " "Info: 3: + IC(0.000 ns) + CELL(0.878 ns) = 3.635 ns; Loc. = DSPOUT_X11_Y1_N0; Fanout = 1; COMB Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|result\[4\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.193 ns) + CELL(2.404 ns) 8.232 ns result\[4\] 4 PIN PIN_B15 0 " "Info: 4: + IC(2.193 ns) + CELL(2.404 ns) = 8.232 ns; Loc. = PIN_B15; Fanout = 0; PIN Node = 'result\[4\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.597 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] result[4] } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.039 ns ( 73.36 % ) " "Info: Total cell delay = 6.039 ns ( 73.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.193 ns ( 26.64 % ) " "Info: Total interconnect delay = 2.193 ns ( 26.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.232 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] result[4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.232 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] result[4] } { 0.000ns 0.000ns 0.000ns 2.193ns } { 0.000ns 2.757ns 0.878ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.414 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.414 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.968ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.232 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] result[4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.232 ns" { lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4] result[4] } { 0.000ns 0.000ns 0.000ns 2.193ns } { 0.000ns 2.757ns 0.878ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 datab\[0\] clock -1.869 ns register " "Info: th for register \"lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0\" (data pin = \"datab\[0\]\", clock pin = \"clock\") is -1.869 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.414 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clock 1 CLK PIN_Y15 18 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.968 ns) 3.414 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 2 REG DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(1.359 ns) + CELL(0.968 ns) = 3.414 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.327 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.055 ns ( 60.19 % ) " "Info: Total cell delay = 2.055 ns ( 60.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.359 ns ( 39.81 % ) " "Info: Total interconnect delay = 1.359 ns ( 39.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.414 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.414 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.968ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.067 ns + " "Info: + Micro hold delay of destination is 0.067 ns" {  } { { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.350 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns datab\[0\] 1 PIN PIN_AA16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA16; Fanout = 1; PIN Node = 'datab\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { datab[0] } "NODE_NAME" } } { "mult.vhd" "" { Text "D:/my_eda2/lpm_mult/mult.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.873 ns) + CELL(0.390 ns) 5.350 ns lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 2 REG DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(3.873 ns) + CELL(0.390 ns) = 5.350 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.263 ns" { datab[0] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "db/mult_m5q.tdf" "" { Text "D:/my_eda2/lpm_mult/db/mult_m5q.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.477 ns ( 27.61 % ) " "Info: Total cell delay = 1.477 ns ( 27.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.873 ns ( 72.39 % ) " "Info: Total interconnect delay = 3.873 ns ( 72.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.350 ns" { datab[0] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.350 ns" { datab[0] datab[0]~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 3.873ns } { 0.000ns 1.087ns 0.390ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.414 ns" { clock lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.414 ns" { clock clock~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 1.359ns } { 0.000ns 1.087ns 0.968ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.350 ns" { datab[0] lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.350 ns" { datab[0] datab[0]~out0 lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } { 0.000ns 0.000ns 3.873ns } { 0.000ns 1.087ns 0.390ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 25 15:13:27 2007 " "Info: Processing ended: Wed Apr 25 15:13:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}