mult.tan.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; N/A                                     ; None                                                ; 10.798 ns  ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT7 ; result[1]  ; clock      ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                       ;            ;            ;
+-----------------------------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                    ;
+---------------+-------------+-----------+----------+---------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To                                                                                    ; To Clock ;
+---------------+-------------+-----------+----------+---------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -1.869 ns ; datab[0] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 ; clock    ;
; N/A           ; None        ; -1.882 ns ; datab[6] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT6 ; clock    ;
; N/A           ; None        ; -1.891 ns ; dataa[7] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT7 ; clock    ;
; N/A           ; None        ; -1.985 ns ; datab[4] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT4 ; clock    ;
; N/A           ; None        ; -1.995 ns ; datab[7] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT7 ; clock    ;
; N/A           ; None        ; -1.997 ns ; datab[3] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT3 ; clock    ;
; N/A           ; None        ; -2.016 ns ; dataa[2] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT2 ; clock    ;
; N/A           ; None        ; -2.029 ns ; datab[5] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT5 ; clock    ;
; N/A           ; None        ; -2.037 ns ; datab[2] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT2 ; clock    ;
; N/A           ; None        ; -2.038 ns ; dataa[0] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT0 ; clock    ;
; N/A           ; None        ; -2.106 ns ; datab[1] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT1 ; clock    ;
; N/A           ; None        ; -2.133 ns ; dataa[4] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT4 ; clock    ;
; N/A           ; None        ; -2.242 ns ; dataa[5] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT5 ; clock    ;
; N/A           ; None        ; -2.255 ns ; dataa[6] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT6 ; clock    ;
; N/A           ; None        ; -2.257 ns ; dataa[3] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT3 ; clock    ;
; N/A           ; None        ; -2.373 ns ; dataa[1] ; lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1 ; clock    ;
+---------------+-------------+-----------+----------+---------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 25 15:13:25 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mult -c mult --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clock"
Info: tsu for register "lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1" (data pin = "dataa[1]", clock pin = "clock") is 2.440 ns
    Info: + Longest pin to register delay is 5.858 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V16; Fanout = 1; PIN Node = 'dataa[1]'
        Info: 2: + IC(4.380 ns) + CELL(0.391 ns) = 5.858 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1'
        Info: Total cell delay = 1.478 ns ( 25.23 % )
        Info: Total interconnect delay = 4.380 ns ( 74.77 % )
    Info: + Micro setup delay of destination is 0.000 ns
    Info: - Shortest clock path from clock "clock" to destination register is 3.418 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.359 ns) + CELL(0.972 ns) = 3.418 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAA_REGOUT1'
        Info: Total cell delay = 2.059 ns ( 60.24 % )
        Info: Total interconnect delay = 1.359 ns ( 39.76 % )
Info: tco from clock "clock" to destination pin "result[4]" through register "lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0" is 11.788 ns
    Info: + Longest clock path from clock "clock" to source register is 3.414 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.359 ns) + CELL(0.968 ns) = 3.414 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0'
        Info: Total cell delay = 2.055 ns ( 60.19 % )
        Info: Total interconnect delay = 1.359 ns ( 39.81 % )
    Info: + Micro clock to output delay of source is 0.142 ns
    Info: + Longest register to pin delay is 8.232 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0'
        Info: 2: + IC(0.000 ns) + CELL(2.757 ns) = 2.757 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; COMB Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~DATAOUT15'
        Info: 3: + IC(0.000 ns) + CELL(0.878 ns) = 3.635 ns; Loc. = DSPOUT_X11_Y1_N0; Fanout = 1; COMB Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[4]'
        Info: 4: + IC(2.193 ns) + CELL(2.404 ns) = 8.232 ns; Loc. = PIN_B15; Fanout = 0; PIN Node = 'result[4]'
        Info: Total cell delay = 6.039 ns ( 73.36 % )
        Info: Total interconnect delay = 2.193 ns ( 26.64 % )
Info: th for register "lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0" (data pin = "datab[0]", clock pin = "clock") is -1.869 ns
    Info: + Longest clock path from clock "clock" to destination register is 3.414 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y15; Fanout = 18; CLK Node = 'clock'
        Info: 2: + IC(1.359 ns) + CELL(0.968 ns) = 3.414 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0'
        Info: Total cell delay = 2.055 ns ( 60.19 % )
        Info: Total interconnect delay = 1.359 ns ( 39.81 % )
    Info: + Micro hold delay of destination is 0.067 ns
    Info: - Shortest pin