taxi.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_TH_RESULT" "distance_reg\[1\] stop clk -2.362 ns register " "Info: th for register \"distance_reg\[1\]\" (data pin = \"stop\", clock pin = \"clk\") is -2.362 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.807 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.912 ns) + CELL(0.666 ns) 2.807 ns distance_reg\[1\] 3 REG LCFF_X26_Y14_N1 5 " "Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.807 ns; Loc. = LCFF_X26_Y14_N1; Fanout = 5; REG Node = 'distance_reg\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { clk~clkctrl distance_reg[1] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.56 % ) " "Info: Total cell delay = 1.756 ns ( 62.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.051 ns ( 37.44 % ) " "Info: Total interconnect delay = 1.051 ns ( 37.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.807 ns" { clk clk~clkctrl distance_reg[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.807 ns" { clk clk~combout clk~clkctrl distance_reg[1] } { 0.000ns 0.000ns 0.139ns 0.912ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.475 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns stop 1 PIN PIN_18 17 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 17; PIN Node = 'stop'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { stop } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.922 ns) + CELL(0.370 ns) 4.382 ns distance_reg~3458 2 COMB LCCOMB_X26_Y14_N22 1 " "Info: 2: + IC(2.922 ns) + CELL(0.370 ns) = 4.382 ns; Loc. = LCCOMB_X26_Y14_N22; Fanout = 1; COMB Node = 'distance_reg~3458'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.292 ns" { stop distance_reg~3458 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.623 ns) 5.367 ns distance_reg\[1\]~3459 3 COMB LCCOMB_X26_Y14_N0 1 " "Info: 3: + IC(0.362 ns) + CELL(0.623 ns) = 5.367 ns; Loc. = LCCOMB_X26_Y14_N0; Fanout = 1; COMB Node = 'distance_reg\[1\]~3459'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.985 ns" { distance_reg~3458 distance_reg[1]~3459 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.475 ns distance_reg\[1\] 4 REG LCFF_X26_Y14_N1 5 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 5.475 ns; Loc. = LCFF_X26_Y14_N1; Fanout = 5; REG Node = 'distance_reg\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { distance_reg[1]~3459 distance_reg[1] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 40.02 % ) " "Info: Total cell delay = 2.191 ns ( 40.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.284 ns ( 59.98 % ) " "Info: Total interconnect delay = 3.284 ns ( 59.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.475 ns" { stop distance_reg~3458 distance_reg[1]~3459 distance_reg[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.475 ns" { stop stop~combout distance_reg~3458 distance_reg[1]~3459 distance_reg[1] } { 0.000ns 0.000ns 2.922ns 0.362ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.623ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.807 ns" { clk clk~clkctrl distance_reg[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.807 ns" { clk clk~combout clk~clkctrl distance_reg[1] } { 0.000ns 0.000ns 0.139ns 0.912ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.475 ns" { stop distance_reg~3458 distance_reg[1]~3459 distance_reg[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.475 ns" { stop stop~combout distance_reg~3458 distance_reg[1]~3459 distance_reg[1] } { 0.000ns 0.000ns 2.922ns 0.362ns 0.000ns } { 0.000ns 1.090ns 0.370ns 0.623ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 19 09:51:58 2007 " "Info: Processing ended: Thu Apr 19 09:51:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}