taxi.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "money_reg\[3\]~146 " "Warning: Node \"money_reg\[3\]~146\" is a latch" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register num\[3\] register money_reg\[6\]~_emulated 93.53 MHz 10.692 ns Internal " "Info: Clock \"clk\" has Internal fmax of 93.53 MHz between source register \"num\[3\]\" and destination register \"money_reg\[6\]~_emulated\" (period= 10.692 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.426 ns + Longest register register " "Info: + Longest register to register delay is 10.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[3\] 1 REG LCFF_X24_Y15_N25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y15_N25; Fanout = 3; REG Node = 'num\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { num[3] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.509 ns) + CELL(0.646 ns) 1.155 ns Equal3~41 2 COMB LCCOMB_X24_Y15_N18 12 " "Info: 2: + IC(0.509 ns) + CELL(0.646 ns) = 1.155 ns; Loc. = LCCOMB_X24_Y15_N18; Fanout = 12; COMB Node = 'Equal3~41'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.155 ns" { num[3] Equal3~41 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.694 ns) + CELL(0.596 ns) 2.445 ns Add1~73 3 COMB LCCOMB_X25_Y15_N2 2 " "Info: 3: + IC(0.694 ns) + CELL(0.596 ns) = 2.445 ns; Loc. = LCCOMB_X25_Y15_N2; Fanout = 2; COMB Node = 'Add1~73'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { Equal3~41 Add1~73 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.531 ns Add1~75 4 COMB LCCOMB_X25_Y15_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 2.531 ns; Loc. = LCCOMB_X25_Y15_N4; Fanout = 2; COMB Node = 'Add1~75'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add1~73 Add1~75 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.617 ns Add1~77 5 COMB LCCOMB_X25_Y15_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.617 ns; Loc. = LCCOMB_X25_Y15_N6; Fanout = 2; COMB Node = 'Add1~77'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add1~75 Add1~77 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.703 ns Add1~79 6 COMB LCCOMB_X25_Y15_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.703 ns; Loc. = LCCOMB_X25_Y15_N8; Fanout = 2; COMB Node = 'Add1~79'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add1~77 Add1~79 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.209 ns Add1~80 7 COMB LCCOMB_X25_Y15_N10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.506 ns) = 3.209 ns; Loc. = LCCOMB_X25_Y15_N10; Fanout = 1; COMB Node = 'Add1~80'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add1~79 Add1~80 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.370 ns) 4.252 ns dis~2912 8 COMB LCCOMB_X24_Y15_N28 1 " "Info: 8: + IC(0.673 ns) + CELL(0.370 ns) = 4.252 ns; Loc. = LCCOMB_X24_Y15_N28; Fanout = 1; COMB Node = 'dis~2912'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { Add1~80 dis~2912 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(0.206 ns) 5.121 ns dis~2913 9 COMB LCCOMB_X23_Y15_N2 2 " "Info: 9: + IC(0.663 ns) + CELL(0.206 ns) = 5.121 ns; Loc. = LCCOMB_X23_Y15_N2; Fanout = 2; COMB Node = 'dis~2913'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { dis~2912 dis~2913 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.624 ns) 6.122 ns LessThan0~75 10 COMB LCCOMB_X23_Y15_N0 8 " "Info: 10: + IC(0.377 ns) + CELL(0.624 ns) = 6.122 ns; Loc. = LCCOMB_X23_Y15_N0; Fanout = 8; COMB Node = 'LessThan0~75'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.001 ns" { dis~2913 LessThan0~75 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.370 ns) 7.194 ns process0~217 11 COMB LCCOMB_X23_Y15_N26 7 " "Info: 11: + IC(0.702 ns) + CELL(0.370 ns) = 7.194 ns; Loc. = LCCOMB_X23_Y15_N26; Fanout = 7; COMB Node = 'process0~217'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.072 ns" { LessThan0~75 process0~217 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.621 ns) 8.516 ns Add7~254 12 COMB LCCOMB_X23_Y15_N4 2 " "Info: 12: + IC(0.701 ns) + CELL(0.621 ns) = 8.516 ns; Loc. = LCCOMB_X23_Y15_N4; Fanout = 2; COMB Node = 'Add7~254'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.322 ns" { process0~217 Add7~254 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.602 ns Add7~256 13 COMB LCCOMB_X23_Y15_N6 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 8.602 ns; Loc. = LCCOMB_X23_Y15_N6; Fanout = 2; COMB Node = 'Add7~256'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add7~254 Add7~256 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.688 ns Add7~258 14 COMB LCCOMB_X23_Y15_N8 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 8.688 ns; Loc. = LCCOMB_X23_Y15_N8; Fanout = 2; COMB Node = 'Add7~258'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add7~256 Add7~258 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.774 ns Add7~260 15 COMB LCCOMB_X23_Y15_N10 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 8.774 ns; Loc. = LCCOMB_X23_Y15_N10; Fanout = 2; COMB Node = 'Add7~260'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add7~258 Add7~260 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 9.280 ns Add7~261 16 COMB LCCOMB_X23_Y15_N12 1 " "Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 9.280 ns; Loc. = LCCOMB_X23_Y15_N12; Fanout = 1; COMB Node = 'Add7~261'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add7~260 Add7~261 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.370 ns) 10.318 ns money_reg\[6\]~343 17 COMB LCCOMB_X22_Y15_N30 1 " "Info: 17: + IC(0.668 ns) + CELL(0.370 ns) = 10.318 ns; Loc. = LCCOMB_X22_Y15_N30; Fanout = 1; COMB Node = 'money_reg\[6\]~343'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.038 ns" { Add7~261 money_reg[6]~343 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.426 ns money_reg\[6\]~_emulated 18 REG LCFF_X22_Y15_N31 1 " "Info: 18: + IC(0.000 ns) + CELL(0.108 ns) = 10.426 ns; Loc. = LCFF_X22_Y15_N31; Fanout = 1; REG Node = 'money_reg\[6\]~_emulated'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { money_reg[6]~343 money_reg[6]~_emulated } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.439 ns ( 52.17 % ) " "Info: Total cell delay = 5.439 ns ( 52.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.987 ns ( 47.83 % ) " "Info: Total interconnect delay = 4.987 ns ( 47.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.426 ns" { num[3] Equal3~41 Add1~73 Add1~75 Add1~77 Add1~79 Add1~80 dis~2912 dis~2913 LessThan0~75 process0~217 Add7~254 Add7~256 Add7~258 Add7~260 Add7~261 money_reg[6]~343 money_reg[6]~_emulated } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "10.426 ns" { num[3] Equal3~41 Add1~73 Add1~75 Add1~77 Add1~79 Add1~80 dis~2912 dis~2913 LessThan0~75 process0~217 Add7~254 Add7~256 Add7~258 Add7~260 Add7~261 money_reg[6]~343 money_reg[6]~_emulated } { 0.000ns 0.509ns 0.694ns 0.000ns 0.000ns 0.000ns 0.000ns 0.673ns 0.663ns 0.377ns 0.702ns 0.701ns 0.000ns 0.000ns 0.000ns 0.000ns 0.668ns 0.000ns } { 0.000ns 0.646ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.206ns 0.624ns 0.370ns 0.621ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.808 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.913 ns) + CELL(0.666 ns) 2.808 ns money_reg\[6\]~_emulated 3 REG LCFF_X22_Y15_N31 1 " "Info: 3: + IC(0.913 ns) + CELL(0.666 ns) = 2.808 ns; Loc. = LCFF_X22_Y15_N31; Fanout = 1; REG Node = 'money_reg\[6\]~_emulated'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.579 ns" { clk~clkctrl money_reg[6]~_emulated } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.54 % ) " "Info: Total cell delay = 1.756 ns ( 62.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.052 ns ( 37.46 % ) " "Info: Total interconnect delay = 1.052 ns ( 37.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.808 ns" { clk clk~clkctrl money_reg[6]~_emulated } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.808 ns" { clk clk~combout clk~clkctrl money_reg[6]~_emulated } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.810 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.666 ns) 2.810 ns num\[3\] 3 REG LCFF_X24_Y15_N25 3 " "Info: 3: + IC(0.915 ns) + CELL(0.666 ns) = 2.810 ns; Loc. = LCFF_X24_Y15_N25; Fanout = 3; REG Node = 'num\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl num[3] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.49 % ) " "Info: Total cell delay = 1.756 ns ( 62.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns ( 37.51 % ) " "Info: Total interconnect delay = 1.054 ns ( 37.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { clk clk~clkctrl num[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { clk clk~combout clk~clkctrl num[3] } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.808 ns" { clk clk~clkctrl money_reg[6]~_emulated } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.808 ns" { clk clk~combout clk~clkctrl money_reg[6]~_emulated } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { clk clk~clkctrl num[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { clk clk~combout clk~clkctrl num[3] } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.426 ns" { num[3] Equal3~41 Add1~73 Add1~75 Add1~77 Add1~79 Add1~80 dis~2912 dis~2913 LessThan0~75 process0~217 Add7~254 Add7~256 Add7~258 Add7~260 Add7~261 money_reg[6]~343 money_reg[6]~_emulated } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "10.426 ns" { num[3] Equal3~41 Add1~73 Add1~75 Add1~77 Add1~79 Add1~80 dis~2912 dis~2913 LessThan0~75 process0~217 Add7~254 Add7~256 Add7~258 Add7~260 Add7~261 money_reg[6]~343 money_reg[6]~_emulated } { 0.000ns 0.509ns 0.694ns 0.000ns 0.000ns 0.000ns 0.000ns 0.673ns 0.663ns 0.377ns 0.702ns 0.701ns 0.000ns 0.000ns 0.000ns 0.000ns 0.668ns 0.000ns } { 0.000ns 0.646ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.206ns 0.624ns 0.370ns 0.621ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.808 ns" { clk clk~clkctrl money_reg[6]~_emulated } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.808 ns" { clk clk~combout clk~clkctrl money_reg[6]~_emulated } { 0.000ns 0.000ns 0.139ns 0.913ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { clk clk~clkctrl num[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { clk clk~combout clk~clkctrl num[3] } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}