taxi_top.map.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 18 19:35:28 2007 " "Info: Processing started: Wed Apr 18 19:35:28 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off taxi_top -c taxi_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off taxi_top -c taxi_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "taxi_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file taxi_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 taxi_top " "Info: Found entity 1: taxi_top" {  } { { "taxi_top.bdf" "" { Schematic "D:/my_eda2/taxi/taxi_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "taxi_top " "Info: Elaborating entity \"taxi_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "decoder.vhd 2 1 " "Warning: Using design file decoder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-one " "Info: Found design unit 1: decoder-one" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "D:/my_eda2/taxi/decoder.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:inst1 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:inst1\"" {  } { { "taxi_top.bdf" "inst1" { Schematic "D:/my_eda2/taxi/taxi_top.bdf" { { 200 496 688 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "taxi.vhd 2 1 " "Warning: Using design file taxi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 taxi-one " "Info: Found design unit 1: taxi-one" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 taxi " "Info: Found entity 1: taxi" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "taxi taxi:inst " "Info: Elaborating entity \"taxi\" for hierarchy \"taxi:inst\"" {  } { { "taxi_top.bdf" "inst" { Schematic "D:/my_eda2/taxi/taxi_top.bdf" { { 216 272 464 344 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "money\[0\] taxi.vhd(21) " "Info (10041): Verilog HDL or VHDL info at taxi.vhd(21): inferred latch for \"money\[0\]\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "money\[1\] taxi.vhd(21) " "Info (10041): Verilog HDL or VHDL info at taxi.vhd(21): inferred latch for \"money\[1\]\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." { { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "taxi:inst\|money_reg\[9\] taxi:inst\|money_reg\[9\]~_emulated taxi:inst\|money_reg\[9\]~146 " "Info: Register \"taxi:inst\|money_reg\[9\]\" converted into equivalent circuit using register \"taxi:inst\|money_reg\[9\]~_emulated\" and latch \"taxi:inst\|money_reg\[9\]~146\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "taxi:inst\|money_reg\[6\] taxi:inst\|money_reg\[6\]~_emulated taxi:inst\|money_reg\[9\]~146 " "Info: Register \"taxi:inst\|money_reg\[6\]\" converted into equivalent circuit using register \"taxi:inst\|money_reg\[6\]~_emulated\" and latch \"taxi:inst\|money_reg\[9\]~146\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "taxi:inst\|money_reg\[4\] taxi:inst\|money_reg\[4\]~_emulated taxi:inst\|money_reg\[9\]~146 " "Info: Register \"taxi:inst\|money_reg\[4\]\" converted into equivalent circuit using register \"taxi:inst\|money_reg\[4\]~_emulated\" and latch \"taxi:inst\|money_reg\[9\]~146\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0} { "Info" "IOPT_MLS_CREATED_ALOAD_CCT_SUB" "taxi:inst\|money_reg\[3\] taxi:inst\|money_reg\[3\]~_emulated taxi:inst\|money_reg\[9\]~146 " "Info: Register \"taxi:inst\|money_reg\[3\]\" converted into equivalent circuit using register \"taxi:inst\|money_reg\[3\]~_emulated\" and latch \"taxi:inst\|money_reg\[9\]~146\"" {  } { { "taxi.vhd" "" { Text "D:/my_eda2/taxi/taxi.vhd" 21 -1 0 } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "428 " "Info: Implemented 428 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "405 " "Info: Implemented 405 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 18 19:35:37 2007 " "Info: Processing ended: Wed Apr 18 19:35:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}