taxi_top.tan.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 18.004 ns
From           : pause
To             : taxi:inst|money_reg[6]~_emulated
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.557 ns
From           : decoder:inst1|cnt[1]
To             : seg7[5]
From Clock     : clk20mhz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.998 ns
From           : speedup[0]
To             : taxi:inst|distance_reg[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 93.79 MHz ( period = 10.662 ns )
From           : taxi:inst|num[3]
To             : taxi:inst|money_reg[7]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk20mhz'
Slack          : N/A
Required Time  : None
Actual Time    : 145.03 MHz ( period = 6.895 ns )
From           : decoder:inst1|comb2[4]
To             : decoder:inst1|comb2_d[3]
From Clock     : clk20mhz
To Clock       : clk20mhz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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