taxi_top.map.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; taxi_top.bdf                     ; yes             ; User Block Diagram/Schematic File  ; D:/my_eda2/taxi/taxi_top.bdf ;
; decoder.vhd                      ; yes             ; Other                              ; D:/my_eda2/taxi/decoder.vhd  ;
; taxi.vhd                         ; yes             ; Other                              ; D:/my_eda2/taxi/taxi.vhd     ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Estimated Total logic elements              ; 362      ;
;                                             ;          ;
; Total combinational functions               ; 362      ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 131      ;
;     -- 3 input functions                    ; 115      ;
;     -- <=2 input functions                  ; 116      ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 236      ;
;     -- arithmetic mode                      ; 126      ;
;                                             ;          ;
; Total registers                             ; 143      ;
;     -- Dedicated logic registers            ; 143      ;
;     -- I/O registers                        ; 0        ;
;                                             ;          ;
; I/O pins                                    ; 0        ;
; Maximum fan-out node                        ; clk20mhz ;
; Maximum fan-out                             ; 105      ;
; Total fan-out                               ; 1533     ;
; Average fan-out                             ; 2.90     ;
+---------------------------------------------+----------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name     ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+
; |taxi_top                  ; 362 (0)           ; 143 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |taxi_top               ;
;    |decoder:inst1|         ; 229 (229)         ; 108 (108)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |taxi_top|decoder:inst1 ;
;    |taxi:inst|             ; 133 (133)         ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |taxi_top|taxi:inst     ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 143   ;
; Number of registers using Synchronous Clear  ; 34    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 35    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 79    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |taxi_top|taxi:inst|money_reg[12]   ;
; 4:1                ; 17 bits   ; 34 LEs        ; 17 LEs               ; 17 LEs                 ; Yes        ; |taxi_top|decoder:inst1|comb2[6]    ;
; 4:1                ; 17 bits   ; 34 LEs        ; 17 LEs               ; 17 LEs                 ; Yes        ; |taxi_top|decoder:inst1|comb1[4]    ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |taxi_top|taxi:inst|num[0]          ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |taxi_top|taxi:inst|money_reg[9]    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |taxi_top|taxi:inst|Add0            ;
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |taxi_top|decoder:inst1|Mux3        ;
; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; No         ; |taxi_top|taxi:inst|distance_reg~82 ;
; 7:1                ; 5 bits    ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; No         ; |taxi_top|taxi:inst|dis~41          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 18 19:35:28 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off taxi_top -c taxi_top
Info: Found 1 design units, including 1 entities, in source file taxi_top.bdf
    Info: Found entity 1: taxi_top
Info: Elaborating entity "taxi_top" for the top level hierarchy
Warning: Using design file decoder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: decoder-one
    Info: Found entity 1: decoder
Info: Elaborating entity "decoder" for hierarchy "decoder:inst1"
Warning: Using design file taxi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: taxi-one
    Info: Found entity 1: taxi
Info: Elaborating entity "taxi" for hierarchy "taxi:inst"
Info (10041): Verilog HDL or VHDL info at taxi.vhd(21): inferred latch for "money[0]"
Info (10041): Verilog HDL or VHDL info at taxi.vhd(21): inferred latch for "money[1]"
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "taxi:inst|money_reg[9]" converted into equivalent circuit using register "taxi:inst|money_reg[9]~_emulated" and latch "taxi:inst|money_reg[9]~146"
    Info: Register "taxi:inst|money_reg[6]" converted into equivalent circuit using register "taxi:inst|money_reg[6]~_emulated" and latch "taxi:inst|money_reg[9]~146"
    Info: Register "taxi:inst|money_reg[4]" converted into equivalent circuit using register "taxi:inst|money_reg[4]~_emulated" and latch "taxi:inst|money_reg[9]~146"
    Info: Register "taxi:inst|money_reg[3]" converted into equivalent circuit using register "taxi:inst|money_reg[3]~_emulated" and latch "taxi:inst|money_reg[9]~146"
Info: Implemented 428 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 16 output pins
    Info: Implemented 405 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 143 megabytes of memory during processing
    Info: Processing ended: Wed Apr 18 19:35:37 2007
    Info: Elapsed time: 00:00:09