taxi_top.fit.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Fitter Status : Successful - Wed Apr 18 19:36:00 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : taxi_top
Top-level Entity Name : taxi_top
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 372 / 8,256 ( 5 % )
    Total combinational functions : 356 / 8,256 ( 4 % )
    Dedicated logic registers : 143 / 8,256 ( 2 % )
Total registers : 143
Total pins : 23 / 85 ( 27 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )