clock.qsf

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		clock_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C8T144C8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY clock
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:51:16  APRIL 11, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name VHDL_FILE clock.vhd
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_location_assignment PIN_17 -to clk
set_location_assignment PIN_67 -to clr
set_location_assignment PIN_65 -to en
set_location_assignment PIN_64 -to mode
set_location_assignment PIN_63 -to set
set_location_assignment PIN_72 -to scan[5]
set_location_assignment PIN_71 -to scan[4]
set_location_assignment PIN_70 -to scan[3]
set_location_assignment PIN_69 -to scan[2]
set_location_assignment PIN_137 -to scan[1]
set_location_assignment PIN_139 -to scan[0]
set_location_assignment PIN_113 -to seg[6]
set_location_assignment PIN_112 -to seg[5]
set_location_assignment PIN_101 -to seg[4]
set_location_assignment PIN_100 -to seg[3]
set_location_assignment PIN_99 -to seg[2]
set_location_assignment PIN_97 -to seg[1]
set_location_assignment PIN_96 -to seg[0]
set_global_assignment -name VECTOR_WAVEFORM_FILE clock.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE clock.vwf