clock.hier_info

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

|clock
clk => clk1khz.CLK
clk => count.CLK
clr => comb~1.OUTPUTSELECT
clr => comb~2.IN0
clr => state[0].ACLR
clr => state[1].ACLR
en => comb~2.IN1
en => inc_reg.ENA
en => sec[0].ENA
en => sec[1].ENA
en => sec[2].ENA
en => sec[3].ENA
en => sec[4].ENA
en => sec[5].ENA
en => min[0].ENA
en => min[1].ENA
en => min[2].ENA
en => min[3].ENA
en => min[4].ENA
en => min[5].ENA
en => hour[0].ENA
en => hour[1].ENA
en => hour[2].ENA
en => hour[3].ENA
en => hour[4].ENA
mode => state[0].CLK
mode => state[1].CLK
inc => hour~20.OUTPUTSELECT
inc => hour~21.OUTPUTSELECT
inc => hour~22.OUTPUTSELECT
inc => hour~23.OUTPUTSELECT
inc => hour~24.OUTPUTSELECT
inc => min~19.OUTPUTSELECT
inc => min~20.OUTPUTSELECT
inc => min~21.OUTPUTSELECT
inc => min~22.OUTPUTSELECT
inc => min~23.OUTPUTSELECT
inc => min~24.OUTPUTSELECT
inc => inc_reg~1.OUTPUTSELECT
inc => sec~13.OUTPUTSELECT
inc => sec~14.OUTPUTSELECT
inc => sec~15.OUTPUTSELECT
inc => sec~16.OUTPUTSELECT
inc => sec~17.OUTPUTSELECT
inc => sec~18.OUTPUTSELECT
seg7[0] <= Mux54.DB_MAX_OUTPUT_PORT_TYPE
seg7[1] <= Mux53.DB_MAX_OUTPUT_PORT_TYPE
seg7[2] <= Mux52.DB_MAX_OUTPUT_PORT_TYPE
seg7[3] <= Mux51.DB_MAX_OUTPUT_PORT_TYPE
seg7[4] <= Mux50.DB_MAX_OUTPUT_PORT_TYPE
seg7[5] <= Mux49.DB_MAX_OUTPUT_PORT_TYPE
seg7[6] <= Mux48.DB_MAX_OUTPUT_PORT_TYPE
scan[0] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE
scan[1] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE
scan[2] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE
scan[3] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE
scan[4] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE
scan[5] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE