clock.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_TH_RESULT" "inc_reg inc clk 5.026 ns register " "Info: th for register \"inc_reg\" (data pin = \"inc\", clock pin = \"clk\") is 5.026 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.722 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G1 4 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.970 ns) 5.256 ns clk1hz 4 REG LCFF_X26_Y12_N17 2 " "Info: 4: + IC(0.899 ns) + CELL(0.970 ns) = 5.256 ns; Loc. = LCFF_X26_Y12_N17; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { clk1khz~clkctrl clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.000 ns) 7.149 ns clk1hz~clkctrl 5 COMB CLKCTRL_G4 18 " "Info: 5: + IC(1.893 ns) + CELL(0.000 ns) = 7.149 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 8.722 ns inc_reg 6 REG LCFF_X26_Y13_N13 3 " "Info: 6: + IC(0.907 ns) + CELL(0.666 ns) = 8.722 ns; Loc. = LCFF_X26_Y13_N13; Fanout = 3; REG Node = 'inc_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk1hz~clkctrl inc_reg } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 42.38 % ) " "Info: Total cell delay = 3.696 ns ( 42.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.026 ns ( 57.62 % ) " "Info: Total interconnect delay = 5.026 ns ( 57.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.722 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl inc_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.722 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl inc_reg } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.907ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.002 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inc 1 PIN PIN_18 3 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 3; PIN Node = 'inc'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { inc } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.153 ns) + CELL(0.651 ns) 3.894 ns inc_reg~136 2 COMB LCCOMB_X26_Y13_N12 1 " "Info: 2: + IC(2.153 ns) + CELL(0.651 ns) = 3.894 ns; Loc. = LCCOMB_X26_Y13_N12; Fanout = 1; COMB Node = 'inc_reg~136'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.804 ns" { inc inc_reg~136 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.002 ns inc_reg 3 REG LCFF_X26_Y13_N13 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 4.002 ns; Loc. = LCFF_X26_Y13_N13; Fanout = 3; REG Node = 'inc_reg'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inc_reg~136 inc_reg } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.849 ns ( 46.20 % ) " "Info: Total cell delay = 1.849 ns ( 46.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.153 ns ( 53.80 % ) " "Info: Total interconnect delay = 2.153 ns ( 53.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.002 ns" { inc inc_reg~136 inc_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.002 ns" { inc inc~combout inc_reg~136 inc_reg } { 0.000ns 0.000ns 2.153ns 0.000ns } { 0.000ns 1.090ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.722 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl inc_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.722 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl inc_reg } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.907ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.002 ns" { inc inc_reg~136 inc_reg } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.002 ns" { inc inc~combout inc_reg~136 inc_reg } { 0.000ns 0.000ns 2.153ns 0.000ns } { 0.000ns 1.090ns 0.651ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 12 17:25:46 2007 " "Info: Processing ended: Thu Apr 12 17:25:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0}