📄 clock.tan.qmsg

📁 基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register state\[0\] state\[1\] 360.1 MHz Internal " "Info: Clock \"mode\" Internal fmax is restricted to 360.1 MHz between source register \"state\[0\]\" and destination register \"state\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.749 ns + Longest register register " "Info: + Longest register to register delay is 0.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\] 1 REG LCFF_X26_Y13_N3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y13_N3; Fanout = 14; REG Node = 'state\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.206 ns) 0.641 ns state\[1\]~39 2 COMB LCCOMB_X26_Y13_N28 1 " "Info: 2: + IC(0.435 ns) + CELL(0.206 ns) = 0.641 ns; Loc. = LCCOMB_X26_Y13_N28; Fanout = 1; COMB Node = 'state\[1\]~39'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.641 ns" { state[0] state[1]~39 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.749 ns state\[1\] 3 REG LCFF_X26_Y13_N29 13 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.749 ns; Loc. = LCFF_X26_Y13_N29; Fanout = 13; REG Node = 'state\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { state[1]~39 state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 41.92 % ) " "Info: Total cell delay = 0.314 ns ( 41.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.435 ns ( 58.08 % ) " "Info: Total interconnect delay = 0.435 ns ( 58.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.749 ns" { state[0] state[1]~39 state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "0.749 ns" { state[0] state[1]~39 state[1] } { 0.000ns 0.435ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 2.874 ns + Shortest register " "Info: + Shortest clock path from clock \"mode\" to destination register is 2.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns mode 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'mode'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.170 ns) + CELL(0.187 ns) 1.301 ns mode~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G7 1 " "Info: 2: + IC(0.170 ns) + CELL(0.187 ns) = 1.301 ns; Loc. = CLKDELAYCTRL_G7; Fanout = 1; COMB Node = 'mode~clk_delay_ctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { mode mode~clk_delay_ctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.301 ns mode~clkctrl 3 COMB CLKCTRL_G7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.301 ns; Loc. = CLKCTRL_G7; Fanout = 2; COMB Node = 'mode~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { mode~clk_delay_ctrl mode~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 2.874 ns state\[1\] 4 REG LCFF_X26_Y13_N29 13 " "Info: 4: + IC(0.907 ns) + CELL(0.666 ns) = 2.874 ns; Loc. = LCFF_X26_Y13_N29; Fanout = 13; REG Node = 'state\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { mode~clkctrl state[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.797 ns ( 62.53 % ) " "Info: Total cell delay = 1.797 ns ( 62.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.077 ns ( 37.47 % ) " "Info: Total interconnect delay = 1.077 ns ( 37.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[1] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 2.874 ns - Longest register " "Info: - Longest clock path from clock \"mode\" to source register is 2.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns mode 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'mode'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.170 ns) + CELL(0.187 ns) 1.301 ns mode~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G7 1 " "Info: 2: + IC(0.170 ns) + CELL(0.187 ns) = 1.301 ns; Loc. = CLKDELAYCTRL_G7; Fanout = 1; COMB Node = 'mode~clk_delay_ctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { mode mode~clk_delay_ctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.301 ns mode~clkctrl 3 COMB CLKCTRL_G7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.301 ns; Loc. = CLKCTRL_G7; Fanout = 2; COMB Node = 'mode~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { mode~clk_delay_ctrl mode~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 2.874 ns state\[0\] 4 REG LCFF_X26_Y13_N3 14 " "Info: 4: + IC(0.907 ns) + CELL(0.666 ns) = 2.874 ns; Loc. = LCFF_X26_Y13_N3; Fanout = 14; REG Node = 'state\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { mode~clkctrl state[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.797 ns ( 62.53 % ) " "Info: Total cell delay = 1.797 ns ( 62.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.077 ns ( 37.47 % ) " "Info: Total interconnect delay = 1.077 ns ( 37.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[0] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[1] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[0] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.749 ns" { state[0] state[1]~39 state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "0.749 ns" { state[0] state[1]~39 state[1] } { 0.000ns 0.435ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[1] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.874 ns" { mode mode~clk_delay_ctrl mode~clkctrl state[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.874 ns" { mode mode~combout mode~clk_delay_ctrl mode~clkctrl state[0] } { 0.000ns 0.000ns 0.170ns 0.000ns 0.907ns } { 0.000ns 0.944ns 0.187ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { state[1] } {  } {  } "" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 57 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "hour\[0\] en clk 2.247 ns register " "Info: tsu for register \"hour\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 2.247 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.007 ns + Longest pin register " "Info: + Longest pin to register delay is 11.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns en 1 PIN PIN_65 5 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_65; Fanout = 5; PIN Node = 'en'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.869 ns) + CELL(0.651 ns) 8.464 ns hour\[4\]~290 2 COMB LCCOMB_X26_Y13_N8 1 " "Info: 2: + IC(6.869 ns) + CELL(0.651 ns) = 8.464 ns; Loc. = LCCOMB_X26_Y13_N8; Fanout = 1; COMB Node = 'hour\[4\]~290'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.520 ns" { en hour[4]~290 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.948 ns) + CELL(0.202 ns) 9.614 ns hour\[4\]~291 3 COMB LCCOMB_X24_Y13_N30 5 " "Info: 3: + IC(0.948 ns) + CELL(0.202 ns) = 9.614 ns; Loc. = LCCOMB_X24_Y13_N30; Fanout = 5; COMB Node = 'hour\[4\]~291'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { hour[4]~290 hour[4]~291 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.855 ns) 11.007 ns hour\[0\] 4 REG LCFF_X25_Y13_N9 5 " "Info: 4: + IC(0.538 ns) + CELL(0.855 ns) = 11.007 ns; Loc. = LCFF_X25_Y13_N9; Fanout = 5; REG Node = 'hour\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.393 ns" { hour[4]~291 hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.652 ns ( 24.09 % ) " "Info: Total cell delay = 2.652 ns ( 24.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.355 ns ( 75.91 % ) " "Info: Total interconnect delay = 8.355 ns ( 75.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.007 ns" { en hour[4]~290 hour[4]~291 hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.007 ns" { en en~combout hour[4]~290 hour[4]~291 hour[0] } { 0.000ns 0.000ns 6.869ns 0.948ns 0.538ns } { 0.000ns 0.944ns 0.651ns 0.202ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.720 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G1 4 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.970 ns) 5.256 ns clk1hz 4 REG LCFF_X26_Y12_N17 2 " "Info: 4: + IC(0.899 ns) + CELL(0.970 ns) = 5.256 ns; Loc. = LCFF_X26_Y12_N17; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { clk1khz~clkctrl clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.000 ns) 7.149 ns clk1hz~clkctrl 5 COMB CLKCTRL_G4 18 " "Info: 5: + IC(1.893 ns) + CELL(0.000 ns) = 7.149 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 8.720 ns hour\[0\] 6 REG LCFF_X25_Y13_N9 5 " "Info: 6: + IC(0.905 ns) + CELL(0.666 ns) = 8.720 ns; Loc. = LCFF_X25_Y13_N9; Fanout = 5; REG Node = 'hour\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 42.39 % ) " "Info: Total cell delay = 3.696 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.024 ns ( 57.61 % ) " "Info: Total interconnect delay = 5.024 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.720 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.720 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.905ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.007 ns" { en hour[4]~290 hour[4]~291 hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.007 ns" { en en~combout hour[4]~290 hour[4]~291 hour[0] } { 0.000ns 0.000ns 6.869ns 0.948ns 0.538ns } { 0.000ns 0.944ns 0.651ns 0.202ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.720 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.720 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.905ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[6\] sec\[3\] 22.756 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[6\]\" through register \"sec\[3\]\" is 22.756 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.719 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G1 4 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.970 ns) 5.256 ns clk1hz 4 REG LCFF_X26_Y12_N17 2 " "Info: 4: + IC(0.899 ns) + CELL(0.970 ns) = 5.256 ns; Loc. = LCFF_X26_Y12_N17; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { clk1khz~clkctrl clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.000 ns) 7.149 ns clk1hz~clkctrl 5 COMB CLKCTRL_G4 18 " "Info: 5: + IC(1.893 ns) + CELL(0.000 ns) = 7.149 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.666 ns) 8.719 ns sec\[3\] 6 REG LCFF_X24_Y13_N3 13 " "Info: 6: + IC(0.904 ns) + CELL(0.666 ns) = 8.719 ns; Loc. = LCFF_X24_Y13_N3; Fanout = 13; REG Node = 'sec\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { clk1hz~clkctrl sec[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 42.39 % ) " "Info: Total cell delay = 3.696 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.023 ns ( 57.61 % ) " "Info: Total interconnect delay = 5.023 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.719 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.719 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[3] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.904ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.733 ns + Longest register pin " "Info: + Longest register to pin delay is 13.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sec\[3\] 1 REG LCFF_X24_Y13_N3 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y13_N3; Fanout = 13; REG Node = 'sec\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sec[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.623 ns) 2.231 ns Mux25~23 2 COMB LCCOMB_X25_Y14_N12 1 " "Info: 2: + IC(1.608 ns) + CELL(0.623 ns) = 2.231 ns; Loc. = LCCOMB_X25_Y14_N12; Fanout = 1; COMB Node = 'Mux25~23'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.231 ns" { sec[3] Mux25~23 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.319 ns) 3.643 ns data~5 3 COMB LCCOMB_X26_Y13_N18 1 " "Info: 3: + IC(1.093 ns) + CELL(0.319 ns) = 3.643 ns; Loc. = LCCOMB_X26_Y13_N18; Fanout = 1; COMB Node = 'data~5'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.412 ns" { Mux25~23 data~5 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.651 ns) 5.398 ns Mux40~572 4 COMB LCCOMB_X25_Y12_N22 1 " "Info: 4: + IC(1.104 ns) + CELL(0.651 ns) = 5.398 ns; Loc. = LCCOMB_X25_Y12_N22; Fanout = 1; COMB Node = 'Mux40~572'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.755 ns" { data~5 Mux40~572 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.206 ns) 6.002 ns Mux40~573 5 COMB LCCOMB_X25_Y12_N10 1 " "Info: 5: + IC(0.398 ns) + CELL(0.206 ns) = 6.002 ns; Loc. = LCCOMB_X25_Y12_N10; Fanout = 1; COMB Node = 'Mux40~573'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.604 ns" { Mux40~572 Mux40~573 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.651 ns) 7.046 ns Mux40~576 6 COMB LCCOMB_X25_Y12_N28 7 " "Info: 6: + IC(0.393 ns) + CELL(0.651 ns) = 7.046 ns; Loc. = LCCOMB_X25_Y12_N28; Fanout = 7; COMB Node = 'Mux40~576'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { Mux40~573 Mux40~576 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.650 ns) 8.835 ns Mux48~21 7 COMB LCCOMB_X29_Y12_N8 1 " "Info: 7: + IC(1.139 ns) + CELL(0.650 ns) = 8.835 ns; Loc. = LCCOMB_X29_Y12_N8; Fanout = 1; COMB Node = 'Mux48~21'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.789 ns" { Mux40~576 Mux48~21 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.672 ns) + CELL(3.226 ns) 13.733 ns seg7\[6\] 8 PIN PIN_115 0 " "Info: 8: + IC(1.672 ns) + CELL(3.226 ns) = 13.733 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'seg7\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.898 ns" { Mux48~21 seg7[6] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.326 ns ( 46.06 % ) " "Info: Total cell delay = 6.326 ns ( 46.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.407 ns ( 53.94 % ) " "Info: Total interconnect delay = 7.407 ns ( 53.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.733 ns" { sec[3] Mux25~23 data~5 Mux40~572 Mux40~573 Mux40~576 Mux48~21 seg7[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "13.733 ns" { sec[3] Mux25~23 data~5 Mux40~572 Mux40~573 Mux40~576 Mux48~21 seg7[6] } { 0.000ns 1.608ns 1.093ns 1.104ns 0.398ns 0.393ns 1.139ns 1.672ns } { 0.000ns 0.623ns 0.319ns 0.651ns 0.206ns 0.651ns 0.650ns 3.226ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.719 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.719 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[3] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.904ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "13.733 ns" { sec[3] Mux25~23 data~5 Mux40~572 Mux40~573 Mux40~576 Mux48~21 seg7[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "13.733 ns" { sec[3] Mux25~23 data~5 Mux40~572 Mux40~573 Mux40~576 Mux48~21 seg7[6] } { 0.000ns 1.608ns 1.093ns 1.104ns 0.398ns 0.393ns 1.139ns 1.672ns } { 0.000ns 0.623ns 0.319ns 0.651ns 0.206ns 0.651ns 0.650ns 3.226ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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