clock.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "mode " "Info: Assuming node \"mode\" is an undefined clock" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 8 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock \"clk1khz\" as buffer" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk1hz " "Info: Detected ripple clock \"clk1hz\" as buffer" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sec\[2\] register hour\[0\] 209.78 MHz 4.767 ns Internal " "Info: Clock \"clk\" has Internal fmax of 209.78 MHz between source register \"sec\[2\]\" and destination register \"hour\[0\]\" (period= 4.767 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.504 ns + Longest register register " "Info: + Longest register to register delay is 4.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sec\[2\] 1 REG LCFF_X24_Y13_N27 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y13_N27; Fanout = 12; REG Node = 'sec\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { sec[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.202 ns) 1.304 ns Equal2~57 2 COMB LCCOMB_X24_Y13_N8 5 " "Info: 2: + IC(1.102 ns) + CELL(0.202 ns) = 1.304 ns; Loc. = LCCOMB_X24_Y13_N8; Fanout = 5; COMB Node = 'Equal2~57'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { sec[2] Equal2~57 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.370 ns) 2.087 ns Equal2~58 3 COMB LCCOMB_X24_Y13_N4 2 " "Info: 3: + IC(0.413 ns) + CELL(0.370 ns) = 2.087 ns; Loc. = LCCOMB_X24_Y13_N4; Fanout = 2; COMB Node = 'Equal2~58'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { Equal2~57 Equal2~58 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.624 ns) 3.111 ns hour\[4\]~291 4 COMB LCCOMB_X24_Y13_N30 5 " "Info: 4: + IC(0.400 ns) + CELL(0.624 ns) = 3.111 ns; Loc. = LCCOMB_X24_Y13_N30; Fanout = 5; COMB Node = 'hour\[4\]~291'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.024 ns" { Equal2~58 hour[4]~291 } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.855 ns) 4.504 ns hour\[0\] 5 REG LCFF_X25_Y13_N9 5 " "Info: 5: + IC(0.538 ns) + CELL(0.855 ns) = 4.504 ns; Loc. = LCFF_X25_Y13_N9; Fanout = 5; REG Node = 'hour\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.393 ns" { hour[4]~291 hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.051 ns ( 45.54 % ) " "Info: Total cell delay = 2.051 ns ( 45.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.453 ns ( 54.46 % ) " "Info: Total interconnect delay = 2.453 ns ( 54.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.504 ns" { sec[2] Equal2~57 Equal2~58 hour[4]~291 hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.504 ns" { sec[2] Equal2~57 Equal2~58 hour[4]~291 hour[0] } { 0.000ns 1.102ns 0.413ns 0.400ns 0.538ns } { 0.000ns 0.202ns 0.370ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.720 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G1 4 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.970 ns) 5.256 ns clk1hz 4 REG LCFF_X26_Y12_N17 2 " "Info: 4: + IC(0.899 ns) + CELL(0.970 ns) = 5.256 ns; Loc. = LCFF_X26_Y12_N17; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { clk1khz~clkctrl clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.000 ns) 7.149 ns clk1hz~clkctrl 5 COMB CLKCTRL_G4 18 " "Info: 5: + IC(1.893 ns) + CELL(0.000 ns) = 7.149 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 8.720 ns hour\[0\] 6 REG LCFF_X25_Y13_N9 5 " "Info: 6: + IC(0.905 ns) + CELL(0.666 ns) = 8.720 ns; Loc. = LCFF_X25_Y13_N9; Fanout = 5; REG Node = 'hour\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 42.39 % ) " "Info: Total cell delay = 3.696 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.024 ns ( 57.61 % ) " "Info: Total interconnect delay = 5.024 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.720 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.720 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.905ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.719 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.582 ns clk1khz 2 REG LCFF_X1_Y9_N29 2 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.582 ns; Loc. = LCFF_X1_Y9_N29; Fanout = 2; REG Node = 'clk1khz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk clk1khz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.000 ns) 3.387 ns clk1khz~clkctrl 3 COMB CLKCTRL_G1 4 " "Info: 3: + IC(0.805 ns) + CELL(0.000 ns) = 3.387 ns; Loc. = CLKCTRL_G1; Fanout = 4; COMB Node = 'clk1khz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.970 ns) 5.256 ns clk1hz 4 REG LCFF_X26_Y12_N17 2 " "Info: 4: + IC(0.899 ns) + CELL(0.970 ns) = 5.256 ns; Loc. = LCFF_X26_Y12_N17; Fanout = 2; REG Node = 'clk1hz'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { clk1khz~clkctrl clk1hz } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.000 ns) 7.149 ns clk1hz~clkctrl 5 COMB CLKCTRL_G4 18 " "Info: 5: + IC(1.893 ns) + CELL(0.000 ns) = 7.149 ns; Loc. = CLKCTRL_G4; Fanout = 18; COMB Node = 'clk1hz~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.893 ns" { clk1hz clk1hz~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.666 ns) 8.719 ns sec\[2\] 6 REG LCFF_X24_Y13_N27 12 " "Info: 6: + IC(0.904 ns) + CELL(0.666 ns) = 8.719 ns; Loc. = LCFF_X24_Y13_N27; Fanout = 12; REG Node = 'sec\[2\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { clk1hz~clkctrl sec[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 42.39 % ) " "Info: Total cell delay = 3.696 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.023 ns ( 57.61 % ) " "Info: Total interconnect delay = 5.023 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.719 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.719 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.904ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.720 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.720 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.905ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.719 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.719 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.904ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "D:/my_eda2/clock_2/clock.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.504 ns" { sec[2] Equal2~57 Equal2~58 hour[4]~291 hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "4.504 ns" { sec[2] Equal2~57 Equal2~58 hour[4]~291 hour[0] } { 0.000ns 1.102ns 0.413ns 0.400ns 0.538ns } { 0.000ns 0.202ns 0.370ns 0.624ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.720 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.720 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl hour[0] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.905ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.719 ns" { clk clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.719 ns" { clk clk~combout clk1khz clk1khz~clkctrl clk1hz clk1hz~clkctrl sec[2] } { 0.000ns 0.000ns 0.522ns 0.805ns 0.899ns 1.893ns 0.904ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}