clock.sim.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; |clock|Add5~80       ; |clock|Add5~80       ; combout          ;
; |clock|Add5~80       ; |clock|Add5~81       ; cout             ;
; |clock|Add5~82       ; |clock|Add5~82       ; combout          ;
; |clock|min[0]        ; |clock|min[0]        ; regout           ;
; |clock|state[1]      ; |clock|state[1]      ; regout           ;
; |clock|data~7        ; |clock|data~7        ; combout          ;
; |clock|hour[2]       ; |clock|hour[2]       ; regout           ;
; |clock|hour[3]       ; |clock|hour[3]       ; regout           ;
; |clock|hour[4]       ; |clock|hour[4]       ; regout           ;
; |clock|Mux37~26      ; |clock|Mux37~26      ; combout          ;
; |clock|Mux20~47      ; |clock|Mux20~47      ; combout          ;
; |clock|sec[2]        ; |clock|sec[2]        ; regout           ;
; |clock|sec[3]        ; |clock|sec[3]        ; regout           ;
; |clock|sec[4]        ; |clock|sec[4]        ; regout           ;
; |clock|Mux26~47      ; |clock|Mux26~47      ; combout          ;
; |clock|sec[5]        ; |clock|sec[5]        ; regout           ;
; |clock|Mux26~48      ; |clock|Mux26~48      ; combout          ;
; |clock|data~4        ; |clock|data~4        ; combout          ;
; |clock|Mux19~62      ; |clock|Mux19~62      ; combout          ;
; |clock|min[1]        ; |clock|min[1]        ; regout           ;
; |clock|min[2]        ; |clock|min[2]        ; regout           ;
; |clock|min[3]        ; |clock|min[3]        ; regout           ;
; |clock|min[4]        ; |clock|min[4]        ; regout           ;
; |clock|Mux32~47      ; |clock|Mux32~47      ; combout          ;
; |clock|min[5]        ; |clock|min[5]        ; regout           ;
; |clock|Mux32~48      ; |clock|Mux32~48      ; combout          ;
; |clock|data~11       ; |clock|data~11       ; combout          ;
; |clock|Mux29~41      ; |clock|Mux29~41      ; combout          ;
; |clock|Mux29~42      ; |clock|Mux29~42      ; combout          ;
; |clock|data~8        ; |clock|data~8        ; combout          ;
; |clock|Mux25~23      ; |clock|Mux25~23      ; combout          ;
; |clock|Mux31~23      ; |clock|Mux31~23      ; combout          ;
; |clock|Mux28~41      ; |clock|Mux28~41      ; combout          ;
; |clock|Mux28~42      ; |clock|Mux28~42      ; combout          ;
; |clock|data~9        ; |clock|data~9        ; combout          ;
; |clock|data~194      ; |clock|data~194      ; combout          ;
; |clock|data~195      ; |clock|data~195      ; combout          ;
; |clock|Mux34~20      ; |clock|Mux34~20      ; combout          ;
; |clock|Mux22~41      ; |clock|Mux22~41      ; combout          ;
; |clock|Mux39~543     ; |clock|Mux39~543     ; combout          ;
; |clock|Mux39~544     ; |clock|Mux39~544     ; combout          ;
; |clock|Mux27~29      ; |clock|Mux27~29      ; combout          ;
; |clock|Mux27~30      ; |clock|Mux27~30      ; combout          ;
; |clock|data~10       ; |clock|data~10       ; combout          ;
; |clock|Mux33~16      ; |clock|Mux33~16      ; combout          ;
; |clock|Mux21~30      ; |clock|Mux21~30      ; combout          ;
; |clock|Mux38~607     ; |clock|Mux38~607     ; combout          ;
; |clock|Mux38~608     ; |clock|Mux38~608     ; combout          ;
; |clock|comb~2        ; |clock|comb~2        ; combout          ;
; |clock|Equal2~57     ; |clock|Equal2~57     ; combout          ;
; |clock|Equal2~58     ; |clock|Equal2~58     ; combout          ;
; |clock|min[5]~243    ; |clock|min[5]~243    ; combout          ;
; |clock|Equal1~52     ; |clock|Equal1~52     ; combout          ;
; |clock|Equal1~53     ; |clock|Equal1~53     ; combout          ;
; |clock|Equal0~35     ; |clock|Equal0~35     ; combout          ;
; |clock|Mux13~35      ; |clock|Mux13~35      ; combout          ;
; |clock|Mux12~35      ; |clock|Mux12~35      ; combout          ;
; |clock|sec[5]~162    ; |clock|sec[5]~162    ; combout          ;
; |clock|Mux3~37       ; |clock|Mux3~37       ; combout          ;
; |clock|Mux2~37       ; |clock|Mux2~37       ; combout          ;
; |clock|Mux1~37       ; |clock|Mux1~37       ; combout          ;
; |clock|Mux0~37       ; |clock|Mux0~37       ; combout          ;
; |clock|Mux9~37       ; |clock|Mux9~37       ; combout          ;
; |clock|Mux8~37       ; |clock|Mux8~37       ; combout          ;
; |clock|Mux7~37       ; |clock|Mux7~37       ; combout          ;
; |clock|Mux6~37       ; |clock|Mux6~37       ; combout          ;
; |clock|data~5        ; |clock|data~5        ; combout          ;
; |clock|data~12       ; |clock|data~12       ; combout          ;
; |clock|state[0]~40   ; |clock|state[0]~40   ; combout          ;
; |clock|clr           ; |clock|clr           ; combout          ;
; |clock|en            ; |clock|en            ; combout          ;
; |clock|comb~2clkctrl ; |clock|comb~2clkctrl ; outclk           ;
+----------------------+----------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------+
; Missing 0-Value Coverage                                       ;
+----------------------+----------------------+------------------+
; Node Name            ; Output Port Name     ; Output Port Type ;
+----------------------+----------------------+------------------+
; |clock|Add5~72       ; |clock|Add5~72       ; combout          ;
; |clock|Add5~72       ; |clock|Add5~73       ; cout             ;
; |clock|Add4~62       ; |clock|Add4~63       ; cout             ;
; |clock|Add4~64       ; |clock|Add4~64       ; combout          ;
; |clock|Add4~64       ; |clock|Add4~65       ; cout             ;
; |clock|Add4~66       ; |clock|Add4~66       ; combout          ;
; |clock|Add4~66       ; |clock|Add4~67       ; cout             ;
; |clock|Add4~68       ; |clock|Add4~68       ; combout          ;
; |clock|Add6~74       ; |clock|Add6~75       ; cout             ;
; |clock|Add6~76       ; |clock|Add6~76       ; combout          ;
; |clock|Add6~76       ; |clock|Add6~77       ; cout             ;
; |clock|Add6~78       ; |clock|Add6~78       ; combout          ;
; |clock|Add6~78       ; |clock|Add6~79       ; cout             ;
; |clock|Add6~80       ; |clock|Add6~80       ; combout          ;
; |clock|Add6~80       ; |clock|Add6~81       ; cout             ;
; |clock|Add6~82       ; |clock|Add6~82       ; combout          ;
; |clock|Add5~74       ; |clock|Add5~74       ; combout          ;
; |clock|Add5~74       ; |clock|Add5~75       ; cout             ;
; |clock|Add5~76       ; |clock|Add5~76       ; combout          ;
; |clock|Add5~76       ; |clock|Add5~77       ; cout             ;
; |clock|Add5~78       ; |clock|Add5~78       ; combout          ;
; |clock|Add5~78       ; |clock|Add5~79       ; cout             ;
; |clock|Add5~80       ; |clock|Add5~80       ; combout          ;
; |clock|Add5~80       ; |clock|Add5~81       ; cout             ;
; |clock|Add5~82       ; |clock|Add5~82       ; combout          ;
; |clock|min[0]        ; |clock|min[0]        ; regout           ;
; |clock|state[1]      ; |clock|state[1]      ; regout           ;
; |clock|state[0]      ; |clock|state[0]      ; regout           ;
; |clock|data~7        ; |clock|data~7        ; combout          ;
; |clock|hour[1]       ; |clock|hour[1]       ; regout           ;
; |clock|hour[2]       ; |clock|hour[2]       ; regout           ;
; |clock|hour[3]       ; |clock|hour[3]       ; regout           ;
; |clock|hour[4]       ; |clock|hour[4]       ; regout           ;
; |clock|Mux37~26      ; |clock|Mux37~26      ; combout          ;
; |clock|Mux20~47      ; |clock|Mux20~47      ; combout          ;
; |clock|sec[1]        ; |clock|sec[1]        ; regout           ;
; |clock|sec[2]        ; |clock|sec[2]        ; regout           ;
; |clock|sec[3]        ; |clock|sec[3]        ; regout           ;
; |clock|sec[4]        ; |clock|sec[4]        ; regout           ;
; |clock|Mux26~47      ; |clock|Mux26~47      ; combout          ;
; |clock|sec[5]        ; |clock|sec[5]        ; regout           ;
; |clock|Mux26~48      ; |clock|Mux26~48      ; combout          ;
; |clock|data~4        ; |clock|data~4        ; combout          ;
; |clock|Mux19~62      ; |clock|Mux19~62      ; combout          ;
; |clock|min[1]        ; |clock|min[1]        ; regout           ;
; |clock|min[2]        ; |clock|min[2]        ; regout           ;
; |clock|min[3]        ; |clock|min[3]        ; regout           ;
; |clock|min[4]        ; |clock|min[4]        ; regout           ;
; |clock|Mux32~47      ; |clock|Mux32~47      ; combout          ;
; |clock|min[5]        ; |clock|min[5]        ; regout           ;
; |clock|Mux32~48      ; |clock|Mux32~48      ; combout          ;
; |clock|data~11       ; |clock|data~11       ; combout          ;
; |clock|Mux29~41      ; |clock|Mux29~41      ; combout          ;
; |clock|Mux29~42      ; |clock|Mux29~42      ; combout          ;
; |clock|data~8        ; |clock|data~8        ; combout          ;
; |clock|Mux25~23      ; |clock|Mux25~23      ; combout          ;
; |clock|Mux31~23      ; |clock|Mux31~23      ; combout          ;
; |clock|Mux35~22      ; |clock|Mux35~22      ; combout          ;
; |clock|Mux23~41      ; |clock|Mux23~41      ; combout          ;
; |clock|Mux23~42      ; |clock|Mux23~42      ; combout          ;
; |clock|Mux40~574     ; |clock|Mux40~574     ; combout          ;
; |clock|Mux28~41      ; |clock|Mux28~41      ; combout          ;
; |clock|Mux28~42      ; |clock|Mux28~42      ; combout          ;
; |clock|data~9        ; |clock|data~9        ; combout          ;
; |clock|data~194      ; |clock|data~194      ; combout          ;
; |clock|data~195      ; |clock|data~195      ; combout          ;
; |clock|Mux34~20      ; |clock|Mux34~20      ; combout          ;
; |clock|Mux22~41      ; |clock|Mux22~41      ; combout          ;
; |clock|Mux22~42      ; |clock|Mux22~42      ; combout          ;
; |clock|Mux39~543     ; |clock|Mux39~543     ; combout          ;
; |clock|Mux39~544     ; |clock|Mux39~544     ; combout          ;
; |clock|Mux27~29      ; |clock|Mux27~29      ; combout          ;
; |clock|Mux27~30      ; |clock|Mux27~30      ; combout          ;
; |clock|data~10       ; |clock|data~10       ; combout          ;
; |clock|Mux33~16      ; |clock|Mux33~16      ; combout          ;
; |clock|Mux21~29      ; |clock|Mux21~29      ; combout          ;
; |clock|Mux21~30      ; |clock|Mux21~30      ; combout          ;
; |clock|Mux38~607     ; |clock|Mux38~607     ; combout          ;
; |clock|Mux38~608     ; |clock|Mux38~608     ; combout          ;
; |clock|comb~2        ; |clock|comb~2        ; combout          ;
; |clock|min[5]~242    ; |clock|min[5]~242    ; combout          ;
; |clock|Equal2~57     ; |clock|Equal2~57     ; combout          ;
; |clock|Equal2~58     ; |clock|Equal2~58     ; combout          ;
; |clock|min[5]~243    ; |clock|min[5]~243    ; combout          ;
; |clock|state[1]~39   ; |clock|state[1]~39   ; combout          ;
; |clock|Equal1~52     ; |clock|Equal1~52     ; combout          ;
; |clock|Equal1~53     ; |clock|Equal1~53     ; combout          ;
; |clock|Equal0~35     ; |clock|Equal0~35     ; combout          ;
; |clock|Mux13~35      ; |clock|Mux13~35      ; combout          ;
; |clock|Mux12~35      ; |clock|Mux12~35      ; combout          ;
; |clock|Mux3~37       ; |clock|Mux3~37       ; combout          ;
; |clock|Mux2~37       ; |clock|Mux2~37       ; combout          ;
; |clock|Mux1~37       ; |clock|Mux1~37       ; combout          ;
; |clock|Mux0~37       ; |clock|Mux0~37       ; combout          ;
; |clock|Mux9~37       ; |clock|Mux9~37       ; combout          ;
; |clock|Mux8~37       ; |clock|Mux8~37       ; combout          ;
; |clock|Mux7~37       ; |clock|Mux7~37       ; combout          ;
; |clock|Mux6~37       ; |clock|Mux6~37       ; combout          ;
; |clock|inc_reg~135   ; |clock|inc_reg~135   ; combout          ;
; |clock|data~5        ; |clock|data~5        ; combout          ;
; |clock|data~12       ; |clock|data~12       ; combout          ;
; |clock|clr           ; |clock|clr           ; combout          ;
; |clock|en            ; |clock|en            ; combout          ;
; |clock|comb~2clkctrl ; |clock|comb~2clkctrl ; outclk           ;
+----------------------+----------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Apr 13 10:12:49 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off clock -c clock
Info: Using vector source file "D:/my_eda2/clock_2/clock.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of clock.vwf called clock.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      41.44 %
Info: Number of transitions in simulation is 24221
Info: Vector file clock.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 90 megabytes of memory during processing
    Info: Processing ended: Fri Apr 13 10:12:50 2007
    Info: Elapsed time: 00:00:01