clock.tan.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.247 ns
From           : en
To             : hour[4]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 22.756 ns
From           : sec[3]
To             : seg7[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.026 ns
From           : inc
To             : inc_reg
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 209.78 MHz ( period = 4.767 ns )
From           : sec[2]
To             : hour[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'mode'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 360.10 MHz ( period = 2.777 ns )
From           : state[0]
To             : state[1]
From Clock     : mode
To Clock       : mode
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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