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📄 clock.vwf

📁 基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）
💻 VWF
📖 第 1 页 / 共 3 页
字号:
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123 

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		LEVEL 0 FOR 37.376;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 2.259;
		LEVEL 1 FOR 1.623;
		LEVEL 0 FOR 15.294;
		LEVEL 1 FOR 20.824;
		LEVEL 0 FOR 21.208;
		LEVEL 1 FOR 0.621;
		LEVEL 0 FOR 0.174;
		LEVEL 1 FOR 0.621;
		LEVEL 0 FOR 37.376;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 2.259;
		LEVEL 1 FOR 1.623;
		LEVEL 0 FOR 15.294;
		LEVEL 1 FOR 20.824;
		LEVEL 0 FOR 21.208;
		LEVEL 1 FOR 0.621;
		LEVEL 0 FOR 0.174;
		LEVEL 1 FOR 0.621;
		LEVEL 0 FOR 37.376;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 2.259;
		LEVEL 1 FOR 1.623;
		LEVEL 0 FOR 15.294;
123

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