📄 ping_pang.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1khz " "Info: Assuming node \"clk1khz\" is an undefined clock" { } { { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 5 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1_2hz " "Info: Detected ripple clock \"clk1_2hz\" as buffer" { } { { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 14 -1 0 } } { "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus ii7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1_2hz" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1khz register shift_1\[0\] register shift_1\[11\] 146.69 MHz 6.817 ns Internal " "Info: Clock \"clk1khz\" has Internal fmax of 146.69 MHz between source register \"shift_1\[0\]\" and destination register \"shift_1\[11\]\" (period= 6.817 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.553 ns + Longest register register " "Info: + Longest register to register delay is 6.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_1\[0\] 1 REG LCFF_X15_Y15_N31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 5; REG Node = 'shift_1\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_1[0] } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.370 ns) 1.496 ns Equal1~175 2 COMB LCCOMB_X14_Y15_N26 1 " "Info: 2: + IC(1.126 ns) + CELL(0.370 ns) = 1.496 ns; Loc. = LCCOMB_X14_Y15_N26; Fanout = 1; COMB Node = 'Equal1~175'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { shift_1[0] Equal1~175 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.206 ns) 2.716 ns Equal1~176 3 COMB LCCOMB_X14_Y15_N12 3 " "Info: 3: + IC(1.014 ns) + CELL(0.206 ns) = 2.716 ns; Loc. = LCCOMB_X14_Y15_N12; Fanout = 3; COMB Node = 'Equal1~176'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.220 ns" { Equal1~175 Equal1~176 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.647 ns) 3.797 ns LessThan0~159 4 COMB LCCOMB_X14_Y15_N24 3 " "Info: 4: + IC(0.434 ns) + CELL(0.647 ns) = 3.797 ns; Loc. = LCCOMB_X14_Y15_N24; Fanout = 3; COMB Node = 'LessThan0~159'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.081 ns" { Equal1~176 LessThan0~159 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus ii7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.370 ns) 4.567 ns shift_1\[1\]~5210 5 COMB LCCOMB_X14_Y15_N2 1 " "Info: 5: + IC(0.400 ns) + CELL(0.370 ns) = 4.567 ns; Loc. = LCCOMB_X14_Y15_N2; Fanout = 1; COMB Node = 'shift_1\[1\]~5210'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { LessThan0~159 shift_1[1]~5210 } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.206 ns) 5.140 ns shift_1\[1\]~5213 6 COMB LCCOMB_X14_Y15_N30 14 " "Info: 6: + IC(0.367 ns) + CELL(0.206 ns) = 5.140 ns; Loc. = LCCOMB_X14_Y15_N30; Fanout = 14; COMB Node = 'shift_1\[1\]~5213'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.573 ns" { shift_1[1]~5210 shift_1[1]~5213 } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.855 ns) 6.553 ns shift_1\[11\] 7 REG LCFF_X13_Y15_N11 4 " "Info: 7: + IC(0.558 ns) + CELL(0.855 ns) = 6.553 ns; Loc. = LCFF_X13_Y15_N11; Fanout = 4; REG Node = 'shift_1\[11\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.413 ns" { shift_1[1]~5213 shift_1[11] } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.654 ns ( 40.50 % ) " "Info: Total cell delay = 2.654 ns ( 40.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.899 ns ( 59.50 % ) " "Info: Total interconnect delay = 3.899 ns ( 59.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.553 ns" { shift_1[0] Equal1~175 Equal1~176 LessThan0~159 shift_1[1]~5210 shift_1[1]~5213 shift_1[11] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.553 ns" { shift_1[0] Equal1~175 Equal1~176 LessThan0~159 shift_1[1]~5210 shift_1[1]~5213 shift_1[11] } { 0.000ns 1.126ns 1.014ns 0.434ns 0.400ns 0.367ns 0.558ns } { 0.000ns 0.370ns 0.206ns 0.647ns 0.370ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1khz destination 5.432 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1khz\" to destination register is 5.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk1khz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk1khz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1khz } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk1khz~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk1khz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.970 ns) 3.079 ns clk1_2hz 3 REG LCFF_X33_Y10_N7 2 " "Info: 3: + IC(0.880 ns) + CELL(0.970 ns) = 3.079 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 2; REG Node = 'clk1_2hz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { clk1khz~clkctrl clk1_2hz } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.000 ns) 3.835 ns clk1_2hz~clkctrl 4 COMB CLKCTRL_G7 26 " "Info: 4: + IC(0.756 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G7; Fanout = 26; COMB Node = 'clk1_2hz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.756 ns" { clk1_2hz clk1_2hz~clkctrl } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.666 ns) 5.432 ns shift_1\[11\] 5 REG LCFF_X13_Y15_N11 4 " "Info: 5: + IC(0.931 ns) + CELL(0.666 ns) = 5.432 ns; Loc. = LCFF_X13_Y15_N11; Fanout = 4; REG Node = 'shift_1\[11\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { clk1_2hz~clkctrl shift_1[11] } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 50.18 % ) " "Info: Total cell delay = 2.726 ns ( 50.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.706 ns ( 49.82 % ) " "Info: Total interconnect delay = 2.706 ns ( 49.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1khz source 5.432 ns - Longest register " "Info: - Longest clock path from clock \"clk1khz\" to source register is 5.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk1khz 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk1khz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1khz } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk1khz~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk1khz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk1khz clk1khz~clkctrl } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.970 ns) 3.079 ns clk1_2hz 3 REG LCFF_X33_Y10_N7 2 " "Info: 3: + IC(0.880 ns) + CELL(0.970 ns) = 3.079 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 2; REG Node = 'clk1_2hz'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { clk1khz~clkctrl clk1_2hz } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.000 ns) 3.835 ns clk1_2hz~clkctrl 4 COMB CLKCTRL_G7 26 " "Info: 4: + IC(0.756 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G7; Fanout = 26; COMB Node = 'clk1_2hz~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.756 ns" { clk1_2hz clk1_2hz~clkctrl } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.666 ns) 5.432 ns shift_1\[0\] 5 REG LCFF_X15_Y15_N31 5 " "Info: 5: + IC(0.931 ns) + CELL(0.666 ns) = 5.432 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 5; REG Node = 'shift_1\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { clk1_2hz~clkctrl shift_1[0] } "NODE_NAME" } } { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 50.18 % ) " "Info: Total cell delay = 2.726 ns ( 50.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.706 ns ( 49.82 % ) " "Info: Total interconnect delay = 2.706 ns ( 49.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "ping_pang.vhd" "" { Text "D:/my_eda2/ping_pang/ping_pang.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.553 ns" { shift_1[0] Equal1~175 Equal1~176 LessThan0~159 shift_1[1]~5210 shift_1[1]~5213 shift_1[11] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.553 ns" { shift_1[0] Equal1~175 Equal1~176 LessThan0~159 shift_1[1]~5210 shift_1[1]~5213 shift_1[11] } { 0.000ns 1.126ns 1.014ns 0.434ns 0.400ns 0.367ns 0.558ns } { 0.000ns 0.370ns 0.206ns 0.647ns 0.370ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[11] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.432 ns" { clk1khz clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.432 ns" { clk1khz clk1khz~combout clk1khz~clkctrl clk1_2hz clk1_2hz~clkctrl shift_1[0] } { 0.000ns 0.000ns 0.139ns 0.880ns 0.756ns 0.931ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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