jp4x4_1.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jp4x4_1 is
port(clk:in std_logic;------扫描时钟信号
     start:in std_logic;----开始信号，高电平有效
     kbcol:in std_logic_vector(3 downto 0);----------行扫描信号
     kbrow:out std_logic_vector(3 downto 0);---------列扫描信号
     seg7_out:out std_logic_vector(6 downto 0);------7段显示信号(abcdefg)   
     scan:out std_logic_vector(7 downto 0 ));--------数码管地址选择信号
end;
architecture one of jp4x4_1 is
   signal count:std_logic_vector(1 downto 0);
   signal sta:std_logic_vector(1 downto 0);
   signal seg7:std_logic_vector(6 downto 0);
   signal dat:std_logic_vector(4 downto 0);
   signal fn:std_logic;
begin
	scan<="00000001";-------只使用一个数码管显示
----------------------------循环描计数器
process(clk)
begin
if clk'event and clk='1' then count<=count+1;
end if;
end process;
-----------------------------------------循环列扫描
process(clk)
begin
if clk'event and clk='1' then  
	case count is
	when "00"=>kbrow<="0001";sta<="00";
	when "01"=>kbrow<="0010";sta<="01";
	when "10"=>kbrow<="0100";sta<="10";
	when "11"=>kbrow<="1000";sta<="11";
	when others=>kbrow<="1111";
	end case;
end if;
end process;
-----------------------------------------行扫描译码
process(clk,start)
begin
if start='0' then seg7<="0000000";
elsif clk'event and clk='1' then
	case sta is
	when "00"=>
	   case kbcol is
		   when "0001"=> seg7<="1111001";dat<="00011";---3
		   when "0010"=> seg7<="1101101";dat<="00010";---2
		   when "0100"=> seg7<="0110000";dat<="00001";---1
		   when "1000"=> seg7<="1111110";dat<="00000";---0
		   when others=>seg7<="0000000";dat<="11111";
	   end case;
	when "01"=>
	   case kbcol is
		   when "0001"=> seg7<="1110000"; dat<="00111";---7
		   when "0010"=> seg7<="1011111"; dat<="00110";---6
		   when "0100"=> seg7<="1011011"; dat<="00101";---5
		   when "1000"=> seg7<="0110011"; dat<="00100";---4
		   when others=>seg7<="0000000";dat<="11111";
	   end case;
	when "10"=>
	   case kbcol is
		   when "0001"=> seg7<="0011111"; dat<="01011";---b
		   when "0010"=> seg7<="1110111"; dat<="01010";---a
		   when "0100"=> seg7<="1111011"; dat<="01001";---9
		   when "1000"=> seg7<="1111111"; dat<="01000";---8
		   when others=>seg7<="0000000";dat<="11111";
	   end case;
	when "11"=>
	   case kbcol is
		   when "0001"=> seg7<="1000111"; dat<="01111";---f
		   when "0010"=> seg7<="1001111"; dat<="01110";---e
		   when "0100"=> seg7<="0111101"; dat<="01101";---d
		   when "1000"=> seg7<="1001110"; dat<="01100";---c
		   when others=>seg7<="0000000";dat<="11111";
	   end case;
	when others=>seg7<="0000000";
	end case;
end if;
end process;
fn<=not(dat(0)and dat(1)and dat(2)and dat(3)and dat(4));
         ----------------产生按键标志位，用于存储按键信息
process(fn)
begin
	if fn'event and fn='1' then  --------------按键信息存储
		seg7_out<=seg7;
	end if;
end process;
end;