jp4x4_1.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_TSU_RESULT" "seg7\[5\] kbcol\[3\] clk 7.782 ns register " "Info: tsu for register \"seg7\[5\]\" (data pin = \"kbcol\[3\]\", clock pin = \"clk\") is 7.782 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.623 ns + Longest pin register " "Info: + Longest pin to register delay is 10.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns kbcol\[3\] 1 PIN PIN_60 13 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_60; Fanout = 13; PIN Node = 'kbcol\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { kbcol[3] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.931 ns) + CELL(0.366 ns) 8.241 ns Mux12~30 2 COMB LCCOMB_X14_Y12_N8 8 " "Info: 2: + IC(6.931 ns) + CELL(0.366 ns) = 8.241 ns; Loc. = LCCOMB_X14_Y12_N8; Fanout = 8; COMB Node = 'Mux12~30'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.297 ns" { kbcol[3] Mux12~30 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.624 ns) 9.949 ns Mux20~13 3 COMB LCCOMB_X15_Y12_N26 1 " "Info: 3: + IC(1.084 ns) + CELL(0.624 ns) = 9.949 ns; Loc. = LCCOMB_X15_Y12_N26; Fanout = 1; COMB Node = 'Mux20~13'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.708 ns" { Mux12~30 Mux20~13 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.206 ns) 10.515 ns Mux20~14 4 COMB LCCOMB_X15_Y12_N14 1 " "Info: 4: + IC(0.360 ns) + CELL(0.206 ns) = 10.515 ns; Loc. = LCCOMB_X15_Y12_N14; Fanout = 1; COMB Node = 'Mux20~14'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { Mux20~13 Mux20~14 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.623 ns seg7\[5\] 5 REG LCFF_X15_Y12_N15 1 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 10.623 ns; Loc. = LCFF_X15_Y12_N15; Fanout = 1; REG Node = 'seg7\[5\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Mux20~14 seg7[5] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.248 ns ( 21.16 % ) " "Info: Total cell delay = 2.248 ns ( 21.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.375 ns ( 78.84 % ) " "Info: Total interconnect delay = 8.375 ns ( 78.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.623 ns" { kbcol[3] Mux12~30 Mux20~13 Mux20~14 seg7[5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "10.623 ns" { kbcol[3] kbcol[3]~combout Mux12~30 Mux20~13 Mux20~14 seg7[5] } { 0.000ns 0.000ns 6.931ns 1.084ns 0.360ns 0.000ns } { 0.000ns 0.944ns 0.366ns 0.624ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.801 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.801 ns seg7\[5\] 3 REG LCFF_X15_Y12_N15 1 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N15; Fanout = 1; REG Node = 'seg7\[5\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk~clkctrl seg7[5] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.69 % ) " "Info: Total cell delay = 1.756 ns ( 62.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 37.31 % ) " "Info: Total interconnect delay = 1.045 ns ( 37.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[5] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "10.623 ns" { kbcol[3] Mux12~30 Mux20~13 Mux20~14 seg7[5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "10.623 ns" { kbcol[3] kbcol[3]~combout Mux12~30 Mux20~13 Mux20~14 seg7[5] } { 0.000ns 0.000ns 6.931ns 1.084ns 0.360ns 0.000ns } { 0.000ns 0.944ns 0.366ns 0.624ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.801 ns" { clk clk~clkctrl seg7[5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.801 ns" { clk clk~combout clk~clkctrl seg7[5] } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7_out\[6\] seg7_out\[6\]~reg0 14.510 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7_out\[6\]\" through register \"seg7_out\[6\]~reg0\" is 14.510 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.678 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.970 ns) 3.105 ns dat\[3\] 3 REG LCFF_X15_Y12_N31 1 " "Info: 3: + IC(0.906 ns) + CELL(0.970 ns) = 3.105 ns; Loc. = LCFF_X15_Y12_N31; Fanout = 1; REG Node = 'dat\[3\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { clk~clkctrl dat[3] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.206 ns) 4.040 ns fn~33 4 COMB LCCOMB_X14_Y12_N22 1 " "Info: 4: + IC(0.729 ns) + CELL(0.206 ns) = 4.040 ns; Loc. = LCCOMB_X14_Y12_N22; Fanout = 1; COMB Node = 'fn~33'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.935 ns" { dat[3] fn~33 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.206 ns) 4.600 ns fn~3 5 COMB LCCOMB_X14_Y12_N14 1 " "Info: 5: + IC(0.354 ns) + CELL(0.206 ns) = 4.600 ns; Loc. = LCCOMB_X14_Y12_N14; Fanout = 1; COMB Node = 'fn~3'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { fn~33 fn~3 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.485 ns) + CELL(0.000 ns) 7.085 ns fn~3clkctrl 6 COMB CLKCTRL_G0 7 " "Info: 6: + IC(2.485 ns) + CELL(0.000 ns) = 7.085 ns; Loc. = CLKCTRL_G0; Fanout = 7; COMB Node = 'fn~3clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { fn~3 fn~3clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 8.678 ns seg7_out\[6\]~reg0 7 REG LCFF_X16_Y14_N5 1 " "Info: 7: + IC(0.927 ns) + CELL(0.666 ns) = 8.678 ns; Loc. = LCFF_X16_Y14_N5; Fanout = 1; REG Node = 'seg7_out\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { fn~3clkctrl seg7_out[6]~reg0 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.138 ns ( 36.16 % ) " "Info: Total cell delay = 3.138 ns ( 36.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.540 ns ( 63.84 % ) " "Info: Total interconnect delay = 5.540 ns ( 63.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.678 ns" { clk clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.678 ns" { clk clk~combout clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns 0.729ns 0.354ns 2.485ns 0.927ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.528 ns + Longest register pin " "Info: + Longest register to pin delay is 5.528 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg7_out\[6\]~reg0 1 REG LCFF_X16_Y14_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y14_N5; Fanout = 1; REG Node = 'seg7_out\[6\]~reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg7_out[6]~reg0 } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.482 ns) + CELL(3.046 ns) 5.528 ns seg7_out\[6\] 2 PIN PIN_99 0 " "Info: 2: + IC(2.482 ns) + CELL(3.046 ns) = 5.528 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'seg7_out\[6\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.528 ns" { seg7_out[6]~reg0 seg7_out[6] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.046 ns ( 55.10 % ) " "Info: Total cell delay = 3.046 ns ( 55.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.482 ns ( 44.90 % ) " "Info: Total interconnect delay = 2.482 ns ( 44.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.528 ns" { seg7_out[6]~reg0 seg7_out[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.528 ns" { seg7_out[6]~reg0 seg7_out[6] } { 0.000ns 2.482ns } { 0.000ns 3.046ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.678 ns" { clk clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.678 ns" { clk clk~combout clk~clkctrl dat[3] fn~33 fn~3 fn~3clkctrl seg7_out[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.906ns 0.729ns 0.354ns 2.485ns 0.927ns } { 0.000ns 1.090ns 0.000ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.528 ns" { seg7_out[6]~reg0 seg7_out[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.528 ns" { seg7_out[6]~reg0 seg7_out[6] } { 0.000ns 2.482ns } { 0.000ns 3.046ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dat\[1\] start clk -0.334 ns register " "Info: th for register \"dat\[1\]\" (data pin = \"start\", clock pin = \"clk\") is -0.334 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.797 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.666 ns) 2.797 ns dat\[1\] 3 REG LCFF_X14_Y12_N7 1 " "Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.797 ns; Loc. = LCFF_X14_Y12_N7; Fanout = 1; REG Node = 'dat\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl dat[1] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.78 % ) " "Info: Total cell delay = 1.756 ns ( 62.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.041 ns ( 37.22 % ) " "Info: Total interconnect delay = 1.041 ns ( 37.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { clk clk~clkctrl dat[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.797 ns" { clk clk~combout clk~clkctrl dat[1] } { 0.000ns 0.000ns 0.139ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.437 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns start 1 PIN PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 6; PIN Node = 'start'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.492 ns) + CELL(0.855 ns) 3.437 ns dat\[1\] 2 REG LCFF_X14_Y12_N7 1 " "Info: 2: + IC(1.492 ns) + CELL(0.855 ns) = 3.437 ns; Loc. = LCFF_X14_Y12_N7; Fanout = 1; REG Node = 'dat\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.347 ns" { start dat[1] } "NODE_NAME" } } { "jp4x4_1.vhd" "" { Text "D:/my_eda2/jp4x4_1/jp4x4_1.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.945 ns ( 56.59 % ) " "Info: Total cell delay = 1.945 ns ( 56.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.492 ns ( 43.41 % ) " "Info: Total interconnect delay = 1.492 ns ( 43.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.437 ns" { start dat[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.437 ns" { start start~combout dat[1] } { 0.000ns 0.000ns 1.492ns } { 0.000ns 1.090ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { clk clk~clkctrl dat[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.797 ns" { clk clk~combout clk~clkctrl dat[1] } { 0.000ns 0.000ns 0.139ns 0.902ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.437 ns" { start dat[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.437 ns" { start start~combout dat[1] } { 0.000ns 0.000ns 1.492ns } { 0.000ns 1.090ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 07 15:48:53 2007 " "Info: Processing ended: Sat Apr 07 15:48:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}