jp4x4_1.tan.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; N/A           ; None        ; -6.589 ns ; kbcol[3] ; seg7[5] ; clk      ;
; N/A           ; None        ; -6.604 ns ; kbcol[3] ; seg7[0] ; clk      ;
; N/A           ; None        ; -6.637 ns ; kbcol[3] ; seg7[2] ; clk      ;
; N/A           ; None        ; -6.639 ns ; kbcol[3] ; dat[3]  ; clk      ;
; N/A           ; None        ; -6.644 ns ; kbcol[3] ; seg7[1] ; clk      ;
; N/A           ; None        ; -6.644 ns ; kbcol[3] ; seg7[6] ; clk      ;
; N/A           ; None        ; -6.649 ns ; kbcol[0] ; seg7[4] ; clk      ;
; N/A           ; None        ; -6.805 ns ; kbcol[1] ; seg7[4] ; clk      ;
; N/A           ; None        ; -6.915 ns ; kbcol[3] ; seg7[4] ; clk      ;
+---------------+-------------+-----------+----------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Apr 07 15:48:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jp4x4_1 -c jp4x4_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "dat[3]" as buffer
    Info: Detected ripple clock "dat[4]" as buffer
    Info: Detected gated clock "fn~33" as buffer
    Info: Detected ripple clock "dat[0]" as buffer
    Info: Detected ripple clock "dat[2]" as buffer
    Info: Detected ripple clock "dat[1]" as buffer
    Info: Detected gated clock "fn~3" as buffer
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "sta[0]" and destination register "seg7[2]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.669 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N11; Fanout = 15; REG Node = 'sta[0]'
            Info: 2: + IC(0.492 ns) + CELL(0.206 ns) = 0.698 ns; Loc. = LCCOMB_X15_Y12_N4; Fanout = 1; COMB Node = 'Mux23~13'
            Info: 3: + IC(0.657 ns) + CELL(0.206 ns) = 1.561 ns; Loc. = LCCOMB_X15_Y12_N2; Fanout = 1; COMB Node = 'Mux23~14'
            Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.669 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 1; REG Node = 'seg7[2]'
            Info: Total cell delay = 0.520 ns ( 31.16 % )
            Info: Total interconnect delay = 1.149 ns ( 68.84 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N3; Fanout = 1; REG Node = 'seg7[2]'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N11; Fanout = 15; REG Node = 'sta[0]'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "seg7[4]" and destination pin or register "seg7_out[4]~reg0" for clock "clk" (Hold time is 4.43 ns)
    Info: + Largest clock skew is 5.835 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.636 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.906 ns) + CELL(0.970 ns) = 3.105 ns; Loc. = LCFF_X15_Y12_N31; Fanout = 1; REG Node = 'dat[3]'
            Info: 4: + IC(0.729 ns) + CELL(0.206 ns) = 4.040 ns; Loc. = LCCOMB_X14_Y12_N22; Fanout = 1; COMB Node = 'fn~33'
            Info: 5: + IC(0.354 ns) + CELL(0.206 ns) = 4.600 ns; Loc. = LCCOMB_X14_Y12_N14; Fanout = 1; COMB Node = 'fn~3'
            Info: 6: + IC(2.485 ns) + CELL(0.000 ns) = 7.085 ns; Loc. = CLKCTRL_G0; Fanout = 7; COMB Node = 'fn~3clkctrl'
            Info: 7: + IC(0.885 ns) + CELL(0.666 ns) = 8.636 ns; Loc. = LCFF_X19_Y12_N13; Fanout = 1; REG Node = 'seg7_out[4]~reg0'
            Info: Total cell delay = 3.138 ns ( 36.34 % )
            Info: Total interconnect delay = 5.498 ns ( 63.66 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.801 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N25; Fanout = 1; REG Node = 'seg7[4]'
            Info: Total cell delay = 1.756 ns ( 62.69 % )
            Info: Total interconnect delay = 1.045 ns ( 37.31 % )
    Info: - Micro clock to output delay of source is 0.304 ns
    Info: - Shortest register to register delay is 1.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N25; Fanout = 1; REG Node = 'seg7[4]'
        Info: 2: + IC(1.093 ns) + CELL(0.206 ns) = 1.299 ns; Loc. = LCCOMB_X19_Y12_N12; Fanout = 1; COMB Node = 'seg7_out[4]~reg0feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.407 ns; Loc. = LCFF_X19_Y12_N13; Fanout = 1; REG Node = 'seg7_out[4]~reg0'
        Info: Total cell delay = 0.314 ns ( 22.32 % )
        Info: Total interconnect delay = 1.093 ns ( 77.68 % )
    Info: + Micro hold delay of destination is 0.306 ns
Info: tsu for register "seg7[5]" (data pin = "kbcol[3]", clock pin = "clk") is 7.782 ns
    Info: + Longest pin to register delay is 10.623 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_60; Fanout = 13; PIN Node = 'kbcol[3]'
        Info: 2: + IC(6.931 ns) + CELL(0.366 ns) = 8.241 ns; Loc. = LCCOMB_X14_Y12_N8; Fanout = 8; COMB Node = 'Mux12~30'
        Info: 3: + IC(1.084 ns) + CELL(0.624 ns) = 9.949 ns; Loc. = LCCOMB_X15_Y12_N26; Fanout = 1; COMB Node = 'Mux20~13'
        Info: 4: + IC(0.360 ns) + CELL(0.206 ns) = 10.515 ns; Loc. = LCCOMB_X15_Y12_N14; Fanout = 1; COMB Node = 'Mux20~14'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 10.623 ns; Loc. = LCFF_X15_Y12_N15; Fanout = 1; REG Node = 'seg7[5]'
        Info: Total cell delay = 2.248 ns ( 21.16 % )
        Info: Total interconnect delay = 8.375 ns ( 78.84 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X15_Y12_N15; Fanout = 1; REG Node = 'seg7[5]'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
Info: tco from clock "clk" to destination pin "seg7_out[6]" through register "seg7_out[6]~reg0" is 14.510 ns
    Info: + Longest clock path from clock "clk" to source register is 8.678 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.970 ns) = 3.105 ns; Loc. = LCFF_X15_Y12_N31; Fanout = 1; REG Node = 'dat[3]'
        Info: 4: + IC(0.729 ns) + CELL(0.206 ns) = 4.040 ns; Loc. = LCCOMB_X14_Y12_N22; Fanout = 1; COMB Node = 'fn~33'
        Info: 5: + IC(0.354 ns) + CELL(0.206 ns) = 4.600 ns; Loc. = LCCOMB_X14_Y12_N14; Fanout = 1; COMB Node = 'fn~3'
        Info: 6: + IC(2.485 ns) + CELL(0.000 ns) = 7.085 ns; Loc. = CLKCTRL_G0; Fanout = 7; COMB Node = 'fn~3clkctrl'
        Info: 7: + IC(0.927 ns) + CELL(0.666 ns) = 8.678 ns; Loc. = LCFF_X16_Y14_N5; Fanout = 1; REG Node = 'seg7_out[6]~reg0'
        Info: Total cell delay = 3.138 ns ( 36.16 % )
        Info: Total interconnect delay = 5.540 ns ( 63.84 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.528 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y14_N5; Fanout = 1; REG Node = 'seg7_out[6]~reg0'
        Info: 2: + IC(2.482 ns) + CELL(3.046 ns) = 5.528 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'seg7_out[6]'
        Info: Total cell delay = 3.046 ns ( 55.10 % )
        Info: Total interconnect delay = 2.482 ns ( 44.90 % )
Info: th for register "dat[1]" (data pin = "start", clock pin = "clk") is -0.334 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.797 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.902 ns) + CELL(0.666 ns) = 2.797 ns; Loc. = LCFF_X14_Y12_N7; Fanout = 1; REG Node = 'dat[1]'
        Info: Total cell delay = 1.756 ns ( 62.78 % )
        Info: Total interconnect delay = 1.041 ns ( 37.22 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.437 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 6; PIN Node = 'start'
        Info: 2: + IC(1.492 ns) + CELL(0.855 ns) = 3.437 ns; Loc. = LCFF_X14_Y12_N7; Fanout = 1; REG Node = 'dat[1]'
        Info: Total cell delay = 1.945 ns ( 56.59 % )
        Info: Total interconnect delay = 1.492 ns ( 43.41 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Sat Apr 07 15:48:53 2007
    Info: Elapsed time: 00:00:00