📄 jp4x4_1.tan.rpt
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Classic Timing Analyzer report for jp4x4_1
Sat Apr 07 15:48:53 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. Clock Hold: 'clk'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 7.782 ns ; kbcol[3] ; seg7[5] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 14.510 ns ; seg7_out[6]~reg0 ; seg7_out[6] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.334 ns ; start ; dat[4] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[2] ; clk ; clk ; 0 ;
; Clock Hold: 'clk' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; seg7[4] ; seg7_out[4]~reg0 ; clk ; clk ; 7 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 7 ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[2] ; clk ; clk ; None ; None ; 1.669 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[1] ; clk ; clk ; None ; None ; 1.605 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[6] ; clk ; clk ; None ; None ; 1.604 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[5] ; clk ; clk ; None ; None ; 1.578 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[0] ; clk ; clk ; None ; None ; 1.577 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[4] ; clk ; clk ; None ; None ; 1.574 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[3] ; clk ; clk ; None ; None ; 1.567 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[1] ; clk ; clk ; None ; None ; 1.405 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[5] ; clk ; clk ; None ; None ; 1.376 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[0] ; clk ; clk ; None ; None ; 1.375 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[3] ; clk ; clk ; None ; None ; 1.372 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; seg7[2] ; clk ; clk ; None ; None ; 1.364 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[4] ; clk ; clk ; None ; None ; 1.285 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; seg7[6] ; clk ; clk ; None ; None ; 1.279 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; dat[2] ; clk ; clk ; None ; None ; 1.185 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; sta[1] ; clk ; clk ; None ; None ; 1.129 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; count[1] ; clk ; clk ; None ; None ; 1.108 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; kbrow[0]~reg0 ; clk ; clk ; None ; None ; 1.107 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; kbrow[2]~reg0 ; clk ; clk ; None ; None ; 1.107 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; kbrow[1]~reg0 ; clk ; clk ; None ; None ; 1.105 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; kbrow[3]~reg0 ; clk ; clk ; None ; None ; 1.100 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[1] ; dat[3] ; clk ; clk ; None ; None ; 0.963 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; kbrow[1]~reg0 ; clk ; clk ; None ; None ; 0.950 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; kbrow[3]~reg0 ; clk ; clk ; None ; None ; 0.947 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; kbrow[0]~reg0 ; clk ; clk ; None ; None ; 0.946 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; kbrow[2]~reg0 ; clk ; clk ; None ; None ; 0.944 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; sta[0] ; sta[0] ; clk ; clk ; None ; None ; 0.501 ns ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+---------+------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------+------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; seg7[4] ; seg7_out[4]~reg0 ; clk ; clk ; None ; None ; 1.407 ns ;
; Not operational: Clock Skew > Data Delay ; seg7[5] ; seg7_out[5]~reg0 ; clk ; clk ; None ; None ; 1.465 ns ;
; Not operational: Clock Skew > Data Delay ; seg7[3] ; seg7_out[3]~reg0 ; clk ; clk ; None ; None ; 1.600 ns ;
; Not operational: Clock Skew > Data Delay ; seg7[6] ; seg7_out[6]~reg0 ; clk ; clk ; None ; None ; 1.606 ns ;
; Not operational: Clock Skew > Data Delay ; seg7[1] ; seg7_out[1]~reg0 ; clk ; clk ; None ; None ; 1.981 ns ;
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