📄 jp4x4_1.sim.rpt
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; Total output ports with no 1/0-value coverage ; 402 ;
; Total output ports with no 1-value coverage ; 402 ;
; Total output ports with no 0-value coverage ; 412 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+----------------------------------------------------------------+----------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------+----------------------------------------------------------------+------------------+
; |jp4x4_1|fn~0 ; |jp4x4_1|fn~0 ; out0 ;
; |jp4x4_1|fn~1 ; |jp4x4_1|fn~1 ; out0 ;
; |jp4x4_1|fn~2 ; |jp4x4_1|fn~2 ; out0 ;
; |jp4x4_1|fn~3 ; |jp4x4_1|fn~3 ; out0 ;
; |jp4x4_1|seg7_out[2]~reg0 ; |jp4x4_1|seg7_out[2]~reg0 ; regout ;
; |jp4x4_1|seg7_out[5]~reg0 ; |jp4x4_1|seg7_out[5]~reg0 ; regout ;
; |jp4x4_1|dat[0] ; |jp4x4_1|dat[0] ; regout ;
; |jp4x4_1|dat[1] ; |jp4x4_1|dat[1] ; regout ;
; |jp4x4_1|dat[2] ; |jp4x4_1|dat[2] ; regout ;
; |jp4x4_1|dat[3] ; |jp4x4_1|dat[3] ; regout ;
; |jp4x4_1|dat[4] ; |jp4x4_1|dat[4] ; regout ;
; |jp4x4_1|seg7[0] ; |jp4x4_1|seg7[0] ; regout ;
; |jp4x4_1|seg7[1] ; |jp4x4_1|seg7[1] ; regout ;
; |jp4x4_1|seg7[2] ; |jp4x4_1|seg7[2] ; regout ;
; |jp4x4_1|seg7[3] ; |jp4x4_1|seg7[3] ; regout ;
; |jp4x4_1|seg7[4] ; |jp4x4_1|seg7[4] ; regout ;
; |jp4x4_1|seg7[5] ; |jp4x4_1|seg7[5] ; regout ;
; |jp4x4_1|seg7[6] ; |jp4x4_1|seg7[6] ; regout ;
; |jp4x4_1|sta[0] ; |jp4x4_1|sta[0] ; regout ;
; |jp4x4_1|sta[1] ; |jp4x4_1|sta[1] ; regout ;
; |jp4x4_1|kbrow[0]~reg0 ; |jp4x4_1|kbrow[0]~reg0 ; regout ;
; |jp4x4_1|kbrow[1]~reg0 ; |jp4x4_1|kbrow[1]~reg0 ; regout ;
; |jp4x4_1|kbrow[2]~reg0 ; |jp4x4_1|kbrow[2]~reg0 ; regout ;
; |jp4x4_1|kbrow[3]~reg0 ; |jp4x4_1|kbrow[3]~reg0 ; regout ;
; |jp4x4_1|count[0] ; |jp4x4_1|count[0] ; regout ;
; |jp4x4_1|count[1] ; |jp4x4_1|count[1] ; regout ;
; |jp4x4_1|clk ; |jp4x4_1|clk ; out ;
; |jp4x4_1|kbcol[0] ; |jp4x4_1|kbcol[0] ; out ;
; |jp4x4_1|kbcol[1] ; |jp4x4_1|kbcol[1] ; out ;
; |jp4x4_1|kbcol[2] ; |jp4x4_1|kbcol[2] ; out ;
; |jp4x4_1|kbcol[3] ; |jp4x4_1|kbcol[3] ; out ;
; |jp4x4_1|kbrow[0] ; |jp4x4_1|kbrow[0] ; pin_out ;
; |jp4x4_1|kbrow[1] ; |jp4x4_1|kbrow[1] ; pin_out ;
; |jp4x4_1|kbrow[2] ; |jp4x4_1|kbrow[2] ; pin_out ;
; |jp4x4_1|kbrow[3] ; |jp4x4_1|kbrow[3] ; pin_out ;
; |jp4x4_1|seg7_out[2] ; |jp4x4_1|seg7_out[2] ; pin_out ;
; |jp4x4_1|seg7_out[5] ; |jp4x4_1|seg7_out[5] ; pin_out ;
; |jp4x4_1|Add0~10 ; |jp4x4_1|Add0~10 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~0 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~1 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0]~0 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0]~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~2 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~2 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0]~1 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0]~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0] ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|result_node[0] ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~4 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~4 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~5 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~5 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~6 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~6 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w~0 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~7 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|_~7 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w~1 ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w ; |jp4x4_1|lpm_mux:Mux27|mux_0kc:auto_generated|w_result19w ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~0 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~1 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0]~0 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0]~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~2 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~2 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0]~1 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0]~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0] ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|result_node[0] ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~4 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~4 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~5 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~5 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~6 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|_~6 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w~0 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w~1 ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w ; |jp4x4_1|lpm_mux:Mux26|mux_0kc:auto_generated|w_result19w ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~0 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~1 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0]~0 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0]~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~2 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~2 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~3 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~3 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0]~1 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0]~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0] ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|result_node[0] ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~4 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~4 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~5 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~5 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~6 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~6 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w~0 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~7 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|_~7 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w~1 ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w ; |jp4x4_1|lpm_mux:Mux25|mux_0kc:auto_generated|w_result19w ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~0 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~1 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0]~0 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0]~0 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~2 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~2 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~3 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~3 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0]~1 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0]~1 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0] ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|result_node[0] ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~4 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~4 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~5 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~5 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~6 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|_~6 ; out0 ;
; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|w_result19w~0 ; |jp4x4_1|lpm_mux:Mux24|mux_0kc:auto_generated|w_result19w~0 ; out0 ;
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