lpm_rom.fit.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

+------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; Name      ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+-----------+----------+---------------+---------------+-----------------------+-----+
; q[7]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[6]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[5]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[4]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[3]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[2]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[1]      ; Output   ; --            ; --            ; --                    ; --  ;
; q[0]      ; Output   ; --            ; --            ; --                    ; --  ;
; clk       ; Input    ; 0             ; 0             ; --                    ; --  ;
; adress[0] ; Input    ; 6             ; 6             ; --                    ; --  ;
; adress[1] ; Input    ; 6             ; 6             ; --                    ; --  ;
; adress[2] ; Input    ; 6             ; 6             ; --                    ; --  ;
; adress[3] ; Input    ; 6             ; 6             ; --                    ; --  ;
; adress[4] ; Input    ; 6             ; 6             ; --                    ; --  ;
+-----------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                                                                            ;
+---------------------------------------------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                                                                         ; Pad To Core Index ; Setting ;
+---------------------------------------------------------------------------------------------+-------------------+---------+
; clk                                                                                         ;                   ;         ;
; adress[0]                                                                                   ;                   ;         ;
;      - rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0 ; 0                 ; 6       ;
; adress[1]                                                                                   ;                   ;         ;
;      - rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0 ; 0                 ; 6       ;
; adress[2]                                                                                   ;                   ;         ;
;      - rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0 ; 0                 ; 6       ;
; adress[3]                                                                                   ;                   ;         ;
;      - rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0 ; 0                 ; 6       ;
; adress[4]                                                                                   ;                   ;         ;
;      - rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0 ; 0                 ; 6       ;
+---------------------------------------------------------------------------------------------+-------------------+---------+


+------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                  ;
+------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; clk  ; PIN_17   ; 1       ; Clock ; yes    ; Global Clock         ; GCLK2            ; --                        ;
+------+----------+---------+-------+--------+----------------------+------------------+---------------------------+


+-------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                     ;
+------+----------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+----------------------+------------------+---------------------------+
; clk  ; PIN_17   ; 1       ; Global Clock         ; GCLK2            ; --                        ;
+------+----------+---------+----------------------+------------------+---------------------------+


+------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                          ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Fan-Out ;
+--------------------------------------------------------------------------------+---------+
; adress[4]                                                                      ; 1       ;
; adress[3]                                                                      ; 1       ;
; adress[2]                                                                      ; 1       ;
; adress[1]                                                                      ; 1       ;
; adress[0]                                                                      ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; 1       ;
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; 1       ;
+--------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------+------------+
; Name                                                                               ; Type ; Mode ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF         ; Location   ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------+------------+
; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; Single Clock ; 32           ; 8            ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 256  ; 32                          ; 8                           ; --                          ; --                          ; 256                 ; 1    ; lpm_rom.mif ; M4K_X11_Y4 ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------+------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+----------------------------------------------------+
; Interconnect Usage Summary                         ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage                 ;
+----------------------------+-----------------------+
; Block interconnects        ; 13 / 26,052 ( < 1 % ) ;
; C16 interconnects          ; 2 / 1,156 ( < 1 % )   ;
; C4 interconnects           ; 15 / 17,952 ( < 1 % ) ;
; Direct links