lpm_rom.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk memory memory rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\] 180.05 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 180.05 MHz between source memory \"rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X11_Y4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\] 2 MEM M4K_X11_Y4 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.895 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.815 ns) 2.895 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\] 3 MEM M4K_X11_Y4 1 " "Info: 3: + IC(0.851 ns) + CELL(0.815 ns) = 2.895 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.666 ns" { clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 65.80 % ) " "Info: Total cell delay = 1.905 ns ( 65.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 34.20 % ) " "Info: Total interconnect delay = 0.990 ns ( 34.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.915 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.835 ns) 2.915 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X11_Y4 8 " "Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.686 ns" { clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.04 % ) " "Info: Total cell delay = 1.925 ns ( 66.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 33.96 % ) " "Info: Total interconnect delay = 0.990 ns ( 33.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 adress\[0\] clk 5.229 ns memory " "Info: tsu for memory \"rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0\" (data pin = \"adress\[0\]\", clock pin = \"clk\") is 5.229 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.098 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns adress\[0\] 1 PIN PIN_129 1 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_129; Fanout = 1; PIN Node = 'adress\[0\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { adress[0] } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 112 -24 144 128 "adress\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.998 ns) + CELL(0.176 ns) 8.098 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X11_Y4 8 " "Info: 2: + IC(6.998 ns) + CELL(0.176 ns) = 8.098 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { adress[0] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns ( 13.58 % ) " "Info: Total cell delay = 1.100 ns ( 13.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.998 ns ( 86.42 % ) " "Info: Total interconnect delay = 6.998 ns ( 86.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.098 ns" { adress[0] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.098 ns" { adress[0] adress[0]~combout rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 6.998ns } { 0.000ns 0.924ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.915 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 2.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.835 ns) 2.915 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X11_Y4 8 " "Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.686 ns" { clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.04 % ) " "Info: Total cell delay = 1.925 ns ( 66.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 33.96 % ) " "Info: Total interconnect delay = 0.990 ns ( 33.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.098 ns" { adress[0] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "8.098 ns" { adress[0] adress[0]~combout rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 6.998ns } { 0.000ns 0.924ns 0.176ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\] 9.453 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through memory \"rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\]\" is 9.453 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.895 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.815 ns) 2.895 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\] 3 MEM M4K_X11_Y4 1 " "Info: 3: + IC(0.851 ns) + CELL(0.815 ns) = 2.895 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.666 ns" { clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 65.80 % ) " "Info: Total cell delay = 1.905 ns ( 65.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 34.20 % ) " "Info: Total interconnect delay = 0.990 ns ( 34.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.298 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\] 1 MEM M4K_X11_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.143 ns) + CELL(3.046 ns) 6.298 ns q\[1\] 2 PIN PIN_79 0 " "Info: 2: + IC(3.143 ns) + CELL(3.046 ns) = 6.298 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.189 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] q[1] } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 112 424 600 128 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.155 ns ( 50.10 % ) " "Info: Total cell delay = 3.155 ns ( 50.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.143 ns ( 49.90 % ) " "Info: Total interconnect delay = 3.143 ns ( 49.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.298 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] q[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.298 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] q[1] } { 0.000ns 3.143ns } { 0.109ns 3.046ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.298 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] q[1] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.298 ns" { rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] q[1] } { 0.000ns 3.143ns } { 0.109ns 3.046ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1 adress\[1\] clk -3.822 ns memory " "Info: th for memory \"rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1\" (data pin = \"adress\[1\]\", clock pin = \"clk\") is -3.822 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.915 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 2.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 168 -24 144 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.851 ns) + CELL(0.835 ns) 2.915 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1 3 MEM M4K_X11_Y4 8 " "Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.686 ns" { clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 66.04 % ) " "Info: Total cell delay = 1.925 ns ( 66.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 33.96 % ) " "Info: Total interconnect delay = 0.990 ns ( 33.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.267 ns + " "Info: + Micro hold delay of destination is 0.267 ns" {  } { { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.004 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 7.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns adress\[1\] 1 PIN PIN_52 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'adress\[1\]'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { adress[1] } "NODE_NAME" } } { "lpm_rom.bdf" "" { Schematic "D:/my_eda2/lpm_rom/lpm_rom.bdf" { { 112 -24 144 128 "adress\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.894 ns) + CELL(0.176 ns) 7.004 ns rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1 2 MEM M4K_X11_Y4 8 " "Info: 2: + IC(5.894 ns) + CELL(0.176 ns) = 7.004 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst\|altsyncram:altsyncram_component\|altsyncram_h571:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.070 ns" { adress[1] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_h571.tdf" "" { Text "D:/my_eda2/lpm_rom/db/altsyncram_h571.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.110 ns ( 15.85 % ) " "Info: Total cell delay = 1.110 ns ( 15.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.894 ns ( 84.15 % ) " "Info: Total interconnect delay = 5.894 ns ( 84.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.004 ns" { adress[1] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.004 ns" { adress[1] adress[1]~combout rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 5.894ns } { 0.000ns 0.934ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.915 ns" { clk clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.915 ns" { clk clk~combout clk~clkctrl rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 0.139ns 0.851ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.004 ns" { adress[1] rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.004 ns" { adress[1] adress[1]~combout rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 5.894ns } { 0.000ns 0.934ns 0.176ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}