lpm_rom.hif

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

}
# used_port {
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# end
# entity
lpm_decode
# storage
db|lpm_rom.(10).cnf
db|lpm_rom.(10).cnf
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_decode.tdf
7064aced7099d6822e88da94b7850
6
# user_parameter {
LPM_WIDTH
3
PARAMETER_SIGNED_DEC
USR
LPM_DECODES
8
PARAMETER_SIGNED_DEC
USR
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_aoi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq7
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|declut.inc
b1d5939399e5c04dfe1d209af8cc490
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
}
# end
# entity
decode_aoi
# storage
db|lpm_rom.(11).cnf
db|lpm_rom.(11).cnf
# case_insensitive
# source_file
db|decode_aoi.tdf
403c2b54ef3120f11345a8c9b7f0be95
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
sld_dffex
# storage
db|lpm_rom.(12).cnf
db|lpm_rom.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_SIGNED_DEC
USR
 constraint(d)
0 downto 0
PARAMETER_STRING
USR
 constraint(q)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|lpm_rom.(13).cnf
db|lpm_rom.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
6
PARAMETER_SIGNED_DEC
USR
 constraint(d)
5 downto 0
PARAMETER_STRING
USR
 constraint(q)
5 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|lpm_rom.(14).cnf
db|lpm_rom.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_SIGNED_DEC
USR
 constraint(d)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
4 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_rom_sr
# storage
db|lpm_rom.(15).cnf
db|lpm_rom.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|sld_rom_sr.vhd
61e53a434067f6c2b1b41f60281fc5ff
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
64
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
63 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_rom
# storage
db|lpm_rom.(0).cnf
db|lpm_rom.(0).cnf
# case_insensitive
# source_file
lpm_rom.bdf
1aebbaea7ac7c035a3fcd89f49cb3af
24
# hierarchies {
|
}
# end
# entity
rom
# storage
db|lpm_rom.(1).cnf
db|lpm_rom.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom.vhd
7572cc984d6611b44822d19fc3f157c1
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rom:inst
}
# end
# entity
altsyncram
# storage
db|lpm_rom.(16).cnf
db|lpm_rom.(16).cnf
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altsyncram.tdf
54ca23b6a4929c50f5115a9a53314c
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
lpm_rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_h571
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
rom:inst|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_h571
# storage
db|lpm_rom.(17).cnf
db|lpm_rom.(17).cnf
# case_insensitive
# source_file
db|altsyncram_h571.tdf
8415f1ac9794d14cdfd17a926c6e
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
lpm_rom.mif
2efe6ac27949ef19e7f190c3e6fa3a80
}
# hierarchies {
rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated
}
# end
# complete