lpm_rom.tan.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.229 ns
From           : adress[0]
To             : rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.453 ns
From           : rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1]
To             : q[1]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.822 ns
From           : adress[1]
To             : rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 180.05 MHz ( period = 5.554 ns )
From           : rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4
To             : rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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