lpm_rom.tan.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; N/A           ; None        ; -4.543 ns ; adress[2] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; clk      ;
; N/A           ; None        ; -4.593 ns ; adress[4] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; clk      ;
; N/A           ; None        ; -4.916 ns ; adress[0] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; clk      ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Apr 23 11:02:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lpm_rom -c lpm_rom --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 180.05 MHz between source memory "rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0" and destination memory "rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 3.641 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0'
            Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0]'
            Info: Total cell delay = 3.641 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.020 ns
            Info: + Shortest clock path from clock "clk" to destination memory is 2.895 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.851 ns) + CELL(0.815 ns) = 2.895 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0]'
                Info: Total cell delay = 1.905 ns ( 65.80 % )
                Info: Total interconnect delay = 0.990 ns ( 34.20 % )
            Info: - Longest clock path from clock "clk" to source memory is 2.915 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0'
                Info: Total cell delay = 1.925 ns ( 66.04 % )
                Info: Total interconnect delay = 0.990 ns ( 33.96 % )
        Info: + Micro clock to output delay of source is 0.260 ns
        Info: + Micro setup delay of destination is 0.046 ns
Info: tsu for memory "rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0" (data pin = "adress[0]", clock pin = "clk") is 5.229 ns
    Info: + Longest pin to memory delay is 8.098 ns
        Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_129; Fanout = 1; PIN Node = 'adress[0]'
        Info: 2: + IC(6.998 ns) + CELL(0.176 ns) = 8.098 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.100 ns ( 13.58 % )
        Info: Total interconnect delay = 6.998 ns ( 86.42 % )
    Info: + Micro setup delay of destination is 0.046 ns
    Info: - Shortest clock path from clock "clk" to destination memory is 2.915 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.925 ns ( 66.04 % )
        Info: Total interconnect delay = 0.990 ns ( 33.96 % )
Info: tco from clock "clk" to destination pin "q[1]" through memory "rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1]" is 9.453 ns
    Info: + Longest clock path from clock "clk" to source memory is 2.895 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.851 ns) + CELL(0.815 ns) = 2.895 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1]'
        Info: Total cell delay = 1.905 ns ( 65.80 % )
        Info: Total interconnect delay = 0.990 ns ( 34.20 % )
    Info: + Micro clock to output delay of source is 0.260 ns
    Info: + Longest memory to pin delay is 6.298 ns
        Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y4; Fanout = 1; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1]'
        Info: 2: + IC(3.143 ns) + CELL(3.046 ns) = 6.298 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 3.155 ns ( 50.10 % )
        Info: Total interconnect delay = 3.143 ns ( 49.90 % )
Info: th for memory "rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1" (data pin = "adress[1]", clock pin = "clk") is -3.822 ns
    Info: + Longest clock path from clock "clk" to destination memory is 2.915 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 13; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.851 ns) + CELL(0.835 ns) = 2.915 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 1.925 ns ( 66.04 % )
        Info: Total interconnect delay = 0.990 ns ( 33.96 % )
    Info: + Micro hold delay of destination is 0.267 ns
    Info: - Shortest pin to memory delay is 7.004 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'adress[1]'
        Info: 2: + IC(5.894 ns) + CELL(0.176 ns) = 7.004 ns; Loc. = M4K_X11_Y4; Fanout = 8; MEM Node = 'rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 1.110 ns ( 15.85 % )
        Info: Total interconnect delay = 5.894 ns ( 84.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Mon Apr 23 11:02:17 2007
    Info: Elapsed time: 00:00:02