sin.fit.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

+-------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; clock               ;                   ;         ;
+---------------------+-------------------+---------+


+-------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                   ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; Name  ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
; clock ; PIN_17   ; 7       ; Clock ; yes    ; Global Clock         ; GCLK2            ; --                        ;
+-------+----------+---------+-------+--------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                      ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-------+----------+---------+----------------------+------------------+---------------------------+
; clock ; PIN_17   ; 7       ; Global Clock         ; GCLK2            ; --                        ;
+-------+----------+---------+----------------------+------------------+---------------------------+


+----------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                              ;
+------------------------------------------------------------------------------------+---------+
; Name                                                                               ; Fan-Out ;
+------------------------------------------------------------------------------------+---------+
; cnt:inst2|q1[0]                                                                    ; 3       ;
; cnt:inst2|q1[5]                                                                    ; 2       ;
; cnt:inst2|q1[4]                                                                    ; 2       ;
; cnt:inst2|q1[3]                                                                    ; 2       ;
; cnt:inst2|q1[2]                                                                    ; 2       ;
; cnt:inst2|q1[1]                                                                    ; 2       ;
; cnt:inst2|q1[0]~32                                                                 ; 1       ;
; cnt:inst2|q1[5]~26                                                                 ; 1       ;
; cnt:inst2|q1[4]~30                                                                 ; 1       ;
; cnt:inst2|q1[4]~25                                                                 ; 1       ;
; cnt:inst2|q1[3]~29                                                                 ; 1       ;
; cnt:inst2|q1[3]~24                                                                 ; 1       ;
; cnt:inst2|q1[2]~28                                                                 ; 1       ;
; cnt:inst2|q1[2]~23                                                                 ; 1       ;
; cnt:inst2|q1[1]~27                                                                 ; 1       ;
; cnt:inst2|q1[1]~22                                                                 ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[1] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7] ; 1       ;
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[0] ; 1       ;
+------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+------------+
; Name                                                                                   ; Type ; Mode ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF          ; Location   ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+------------+
; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; Single Clock ; 64           ; 8            ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 512  ; 64                          ; 8                           ; --                          ; --                          ; 512                 ; 1    ; sin_data.mif ; M4K_X11_Y2 ;
+----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+----------------------------------------------------+
; Interconnect Usage Summary                         ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage                 ;
+----------------------------+-----------------------+
; Block interconnects        ; 16 / 26,052 ( < 1 % ) ;
; C16 interconnects          ; 0 / 1,156 ( 0 % )     ;
; C4 interconnects           ; 10 / 17,952 ( < 1 % ) ;
; Direct links               ; 3 / 26,052 ( < 1 % )  ;
; Global clocks              ; 1 / 8 ( 13 % )        ;
; Local interconnects        ; 4 / 8,256 ( < 1 % )   ;
; R24 interconnects          ; 0 / 1,020 ( 0 % )     ;
; R4 interconnects           ; 20 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 6.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 1                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
; 11                                         ; 0                           ;
; 12                                         ; 0                           ;
; 13                                         ; 0                           ;
; 14                                         ; 0