sin_data.mif

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

-- Copyright (C) 1991-2007 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=64;

ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;

CONTENT BEGIN
	0   :   255;
	1   :   254;
	2   :   252;
	3   :   249;
	4   :   245;
	5   :   239;
	6   :   233;
	7   :   225;
	8   :   217;
	9   :   207;
	10  :   197;
	11  :   186;
	12  :   174;
	13  :   162;
	14  :   150;
	15  :   137;
	16  :   124;
	17  :   112;
	18  :   99;
	19  :   87;
	20  :   75;
	21  :   64;
	22  :   53;
	23  :   43;
	24  :   34;
	25  :   26;
	26  :   19;
	27  :   13;
	28  :   8;
	29  :   4;
	30  :   1;
	[31..32]  :   0;
	33  :   1;
	34  :   4;
	35  :   8;
	36  :   13;
	37  :   19;
	38  :   26;
	39  :   34;
	40  :   43;
	41  :   53;
	42  :   64;
	43  :   75;
	44  :   87;
	45  :   99;
	46  :   112;
	47  :   124;
	48  :   137;
	49  :   150;
	50  :   162;
	51  :   174;
	52  :   186;
	53  :   197;
	54  :   207;
	55  :   217;
	56  :   225;
	57  :   233;
	58  :   239;
	59  :   245;
	60  :   249;
	61  :   252;
	62  :   254;
	63  :   255;
END;