cnt.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk:in std_logic;
     q:out std_logic_vector(5 downto 0));
end;
architecture one of cnt is
signal q1:std_logic_vector(5 downto 0);
begin
process(clk)
begin
	if clk'event and clk='1' then
		q1<=q1+1;
	end if;
end process;
q<=q1;
end one;