jiao_tong.sdc

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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# Generated by : Version 7.0 Build 33 02/05/2007 SJ Full Version
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# Project      : jiao_tong
# Revision     : jiao_tong
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# Date         : Sat Mar 31 20:46:46 中国标准时间 2007
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# WARNING: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'
#          In SDC, all clocks are related by default
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
# WARNING: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'
#          In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer
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# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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post_message -type warning "Clock -name {clk} {clk} has no period requirement - check original QSF settings"
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# Entity Specific Timing Assignments found in
# the Timing Analyzer Settings report panel
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