jiao_tong.fnsim.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 16:27:55 2007 " "Info: Processing started: Fri Jun 01 16:27:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jiao_tong -c jiao_tong --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiao_tong -c jiao_tong --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiao_tong.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jiao_tong.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jiao_tong-one " "Info: Found design unit 1: jiao_tong-one" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 jiao_tong " "Info: Found entity 1: jiao_tong" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jiao_tong " "Info: Elaborating entity \"jiao_tong\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data jiao_tong.vhd(185) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(185): inferring latch(es) for signal or variable \"data\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "scan jiao_tong.vhd(185) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(185): inferring latch(es) for signal or variable \"scan\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "scan\[0\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"scan\[0\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "scan\[1\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"scan\[1\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "data\[0\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"data\[0\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "data\[1\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"data\[1\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "data\[2\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"data\[2\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "data\[3\] jiao_tong.vhd(185) " "Info (10041): Verilog HDL or VHDL info at jiao_tong.vhd(185): inferred latch for \"data\[3\]\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 185 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 187 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_0kc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_0kc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_0kc " "Info: Found entity 1: mux_0kc" {  } { { "db/mux_0kc.tdf" "" { Text "D:/my_eda2/jiao_tong/db/mux_0kc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux1\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 187 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux2 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux2\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 187 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux3\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 187 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux4\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_llc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_llc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_llc " "Info: Found entity 1: mux_llc" {  } { { "db/mux_llc.tdf" "" { Text "D:/my_eda2/jiao_tong/db/mux_llc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux5\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux6\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux7 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux7\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux8 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux8\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux9 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux9\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux10 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux10\"" {  } { { "jiao_tong.vhd" "" { Text "D:/my_eda2/jiao_tong/jiao_tong.vhd" 196 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 16:28:04 2007 " "Info: Processing ended: Fri Jun 01 16:28:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}