jiao_tong.sta.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

TimeQuest Timing Analyzer report for jiao_tong
Sat Mar 31 20:47:23 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. SDC File List
  4. Clocks
  5. Fmax Summary
  6. Setup Summary
  7. Hold Summary
  8. Minimum Pulse Width
  9. Setup Transfers
 10. Hold Transfers
 11. Unconstrained Paths
 12. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                    ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name      ; jiao_tong                                       ;
; Device Family      ; Cyclone II                                      ;
; Device Name        ; EP2C8T144C8                                     ;
; Timing Models      ; Final                                           ;
; Delay Model        ; Slow Model                                      ;
; Rise/Fall Delays   ; Unavailable                                     ;
+--------------------+-------------------------------------------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; jiao_tong.sdc ; OK     ; Sat Mar 31 20:47:22 2007 ;
+---------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                 ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; Clock Name ; Type ; Period ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets     ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; clk        ; Base ; 1.000  ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk }     ;
; clk1hz     ; Base ; 1.000  ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk1hz }  ;
; clk1khz    ; Base ; 1.000  ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk1khz } ;
+------------+------+--------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+


+-------------------------+
; Fmax Summary            ;
+------------+------------+
; Fmax (MHz) ; Clock Name ;
+------------+------------+
; 300.48     ; clk1khz    ;
; 272.03     ; clk        ;
; 256.34     ; clk1hz     ;
+------------+------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------+
; Setup Summary                    ;
+---------+--------+---------------+
; Clock   ; Slack  ; End Point TNS ;
+---------+--------+---------------+
; clk1hz  ; -2.901 ; -42.400       ;
; clk     ; -2.676 ; -26.088       ;
; clk1khz ; -2.328 ; -17.114       ;
+---------+--------+---------------+


+---------------------------------+
; Hold Summary                    ;
+---------+-------+---------------+
; Clock   ; Slack ; End Point TNS ;
+---------+-------+---------------+
; clk1khz ; 0.499 ; 0.000         ;
; clk     ; 0.499 ; 0.000         ;
; clk1hz  ; 0.499 ; 0.000         ;
+---------+-------+---------------+


+--------------------------------------------------------------------------------------------+
; Minimum Pulse Width                                                                        ;
+--------+--------------+----------------+-------+---------+------------+--------------------+
; Slack  ; Actual Width ; Required Width ; Pulse ; Clock   ; Clock Edge ; Target             ;
+--------+--------------+----------------+-------+---------+------------+--------------------+
; -0.742 ; 0.500        ; 1.242          ; High  ; clk1khz ; Rise       ; cnt[0]             ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk1khz ; Rise       ; cnt[0]             ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; clk1khz            ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; clk1khz            ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[5]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[5]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[6]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[6]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[4]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[4]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[13]          ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[13]          ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[12]          ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[12]          ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[3]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[3]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk1khz ; Rise       ; \process2:count[4] ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk1khz ; Rise       ; \process2:count[4] ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[7]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[7]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[2]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[2]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[0]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[0]           ;
; -0.742 ; 0.500        ; 1.242          ; High  ; clk     ; Rise       ; count[1]           ;
; -0.742 ; 0.500        ; 1.242          ; Low   ; clk     ; Rise       ; count[1]           ;