jiao_tong.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jiao_tong is
port(clk,jin:in std_logic;
     scan:out std_logic_vector(1 downto 0);
     data_out:out std_logic_vector(6 downto 0);
     ra,rb,ga,gb,ya,yb:out std_logic);
end;
architecture one of jiao_tong is
type states is(st1,st2,st3,st4);
signal clk1khz,clk1hz:std_logic;
signal one,ten:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(1 downto 0);
signal data:std_logic_vector(3 downto 0);
signal data_out1:std_logic_vector(6 downto 0);
signal r1,r2,g1,g2,y1,y2:std_logic;
begin
------------------------------------------
process(clk)
variable count:integer range 0 to 9999;
begin
if clk'event and clk='1' then 
  if count=9999 then clk1khz<=not clk1khz;count:=0;
  else count:=count+1;
  end if;
end if;
end process;
------------------------------------------
process(clk1khz)
variable count:integer range 0 to 499;
begin
if clk1khz'event and clk1khz='1' then 
  if count=499 then clk1hz<=not clk1hz;count:=0;
  else count:=count+1;
  end if;
end if;
end process; 
-------------------------------------------
process(clk1hz)
variable stx:states;
variable a:std_logic;
variable qh,ql:std_logic_vector(3 downto 0);
begin
if clk1hz'event and clk1hz='1' then
case stx is
when st1=>if jin='0' then
             if a='0' then qh:="0011";ql:="0100";a:='1';
	             r1<='0';y1<='0';g1<='1';r2<='1';y2<='0';g2<='0';
	          else if qh=0 and ql=1 then stx:=st2;a:='0';qh:="0000";ql:="0000";
	               elsif ql=0 then ql:="1001";qh:=qh-1;
	               else ql:=ql-1;
	               end if;
	          --else if not(qh=0 and ql=1)then
	          --       if ql=0 then ql:="1001"; qh:=qh-1;
	          --       else ql:=ql-1;end if;
	          --     else qh:="0000";ql:="0000";a:='0';stx:=st2;
	          --     end if;
	          end if;
	      end if;
when st2=>if jin='0' then 
     	      if a='0' then qh:="0000";ql:="0100";a:='1';
	             r1<='0';y1<='1';g1<='0';r2<='1';y2<='0';g2<='0';
	          else if qh=0 and ql=1 then  stx:=st3;a:='0';qh:="0000";ql:="0000";
	               elsif ql=0 then ql:="1001";qh:=qh-1;
	               else ql:=ql-1;
	               end if;
	          --else if not(qh=0 and ql=1)then
	          --       if ql=0 then ql:="1001"; qh:=qh-1;
	          --       else ql:=ql-1;end if;
	          --     else qh:="0000";ql:="0000";a:='0';stx:=st3;
	          --     end if;
	          end if;
	      end if;
when st3=>if jin='0' then 
	          if a='0' then qh:="0010";ql:="0100";a:='1';
	             r1<='1';y1<='0';g1<='0';r2<='0';y2<='0';g2<='1';
	          else if qh=0 and ql=1 then stx:=st4;a:='0';qh:="0000";ql:="0000";
	               elsif ql=0 then ql:="1001";qh:=qh-1;
	               else ql:=ql-1;
	               end if;
	          -- else if not(qh=0 and ql=1)then
	          --       if ql=0 then ql:="1001";qh:=qh-1;
	          --       else ql:=ql-1;end if;
	          --     else qh:="0000";ql:="0000";a:='0';stx:=st4;
	          --     end if;
	          end if;
	      end if;
when st4=>if jin='0' then 
	          if a='0' then qh:="0000";ql:="0100";a:='1';
	             r1<='1';y1<='0';g1<='0';r2<='0';y2<='1';g2<='0';
	          else if qh=0 and ql=1 then  stx:=st1;a:='0';qh:="0000";ql:="0000";
	               elsif ql=0 then ql:="1001";qh:=qh-1;
	               else ql:=ql-1;
	               end if;
	          -- else if not(qh=0 and ql=1)then
	          --       if ql=0 then ql:="1001"; qh:=qh-1;
	          --       else ql:=ql-1;end if;
	          --     else qh:="0000";ql:="0000";a:='0';stx:=st1;
	          --     end if;
	          end if;
	      end if;
end case;
end if;
one<=ql;ten<=qh;
end process;
--------------------------------------------------
process(jin,clk1hz,r1,r2,g1,g2,y1,y2,data_out1)
begin
if jin='1' then ra<=r1 or jin;rb<=r2 or jin;ga<=g1 and not jin;gb<=g2 and not jin;
	ya<=y1 and not jin;yb<=y2 and not jin;
	data_out(0)<=data_out1(0) and clk1hz;
	data_out(1)<=data_out1(1) and clk1hz;
	data_out(2)<=data_out1(2) and clk1hz;
	data_out(3)<=data_out1(3) and clk1hz;
	data_out(4)<=data_out1(4) and clk1hz;
	data_out(5)<=data_out1(5) and clk1hz;
	data_out(6)<=data_out1(6) and clk1hz;
else data_out<=data_out1;ra<=r1;rb<=r2;ga<=g1;gb<=g2;ya<=y1;yb<=y2;
end if;
end process;
---------------------------------------------
process(clk1khz)
begin
if clk1khz'event and clk1khz='1' then  
      if cnt="01" then cnt<="00";
      else cnt<=cnt+1;
      end if;
end if;
end process;
---------------------------------------------------------------
process(cnt,one,ten)
begin
case cnt is
	when "00"=> data<=one;scan<="01";
	when "01"=> data<=ten;scan<="10";
	when others=>null;
end case;
end process;  
-----------------------------------------七段译码--------------------
process(data)
begin
case data is
    when"0000"=>data_out1<="1111110";
	when"0001"=>data_out1<="0110000";
	when"0010"=>data_out1<="1101101";
	when"0011"=>data_out1<="1111001";
	when"0100"=>data_out1<="0110011";
	when"0101"=>data_out1<="1011011";
	when"0110"=>data_out1<="1011111";
	when"0111"=>data_out1<="1110000";
	when"1000"=>data_out1<="1111111";
	when"1001"=>data_out1<="1111011";
    when others=>data_out1<="1001111";
end case;
end process;
end;