mult_inst.v

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· Verilog 代码 · 共 7 行

mult	mult_inst (
	.clock0 ( clock0_sig ),
	.dataa_0 ( dataa_0_sig ),
	.datab_0 ( datab_0_sig ),
	.result ( result_sig )
	);