diff_io_top.tan.summary

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock'
Slack          : 5.994 ns
Required Time  : 105.01 MHz ( period = 9.523 ns )
Actual Time    : 283.37 MHz ( period = 3.529 ns )
From           : mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15
To             : lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]
From Clock     : lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock
To Clock       : lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock
Failed Paths   : 0

Type           : Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1'
Slack          : 7.287 ns
Required Time  : 105.01 MHz ( period = 9.523 ns )
Actual Time    : N/A
From           : lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13]
To             : lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5
From Clock     : lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock
To Clock       : lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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