diff_io_top.fit.summary

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Mon Sep 13 22:27:17 2004
Quartus II Version : 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version
Revision Name : Diff_io_top
Top-level Entity Name : Diff_io_top
Family : Stratix
Device : EP1S10F780C6
Timing Models : Production
Total logic elements : 32 / 10,570 ( < 1 % )
Total pins : 14 / 427 ( 3 % )
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 1 / 48 ( 2 % )
Total PLLs : 1 / 6 ( 16 % )
Total DLLs : 0 / 2 ( 0 % )