diff_io_top.map.summary

altera FPGA/CPLD高级篇(VHDL源代码)

Flow Status : Successful - Mon Sep 13 22:26:55 2004
Quartus II Version : 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version
Revision Name : Diff_io_top
Top-level Entity Name : Diff_io_top
Family : Stratix
Device : EP1S10F780C6
Timing Models : Production
Total logic elements : 32
Total pins : 8
Total memory bits : 0
DSP block 9-bit elements : 1
Total PLLs : 2
Total DLLs : 0