svnseg.tdf

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· TDF 代码 · 共 31 行

SUBDESIGN svnseg
(
	x0,x1,x2,x3	: INPUT;
	a, b, c, d, e, f, g	: OUTPUT;
)


BEGIN
	TABLE
(x3,x2,x1,x0)	=>	a, b, c, d, e, f, g;

		H"0"	=>	1, 1, 1, 1, 1, 1, 0;
		H"1"	=>	0, 1, 1, 0, 0, 0, 0;
		H"2"	=>	1, 1, 0, 1, 1, 0, 1;
		H"3"	=>	1, 1, 1, 1, 0, 0, 1;
		H"4"	=>	0, 1, 1, 0, 0, 1, 1;
		H"5"	=>	1, 0, 1, 1, 0, 1, 1;
		H"6"	=>	1, 0, 1, 1, 1, 1, 1;
		H"7"	=>	1, 1, 1, 0, 0, 0, 0;
		H"8"	=>	1, 1, 1, 1, 1, 1, 1;
		H"9"	=>	1, 1, 1, 1, 0, 1, 1;
		H"A"	=>	1, 1, 1, 0, 1, 1, 1;
		H"B"	=>	0, 0, 1, 1, 1, 1, 1;
		H"C"	=>	1, 0, 0, 1, 1, 1, 0;
		H"D"	=>	0, 1, 1, 1, 1, 0, 1;
		H"E"	=>	1, 0, 0, 1, 1, 1, 1;
		H"F"	=>	1, 0, 0, 0, 1, 1, 1;
	END TABLE;

END;