debounce.v

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· Verilog 代码 · 共 44 行

`define IDLE 'b0
`define DEBOUNCE 'b1

module debounce (input_port, clk, output_port);

input clk, input_port;
output output_port;

reg [19:0] counter;
reg state, nextstate, output_port, lock, input_port_reg;
reg half_clk;

always @ (posedge clk) begin
 input_port_reg = input_port;  
 half_clk = !half_clk;
end

always @ (posedge half_clk) 
  case (state)  
  `IDLE: begin 
       counter = 20'b00000000000000000000;
       if (lock == 1'b1) state = `DEBOUNCE; 
    end
  `DEBOUNCE: begin 
       counter = counter + 1;       
       if (counter == 20'b11111111111111111111) state = `IDLE; 
    end
  default nextstate = `IDLE;
 endcase

always @ (state or input_port_reg) begin
if (state == `IDLE)
    if (input_port_reg == 1'b1) begin
	 	lock = 1'b1;
	  	output_port = 1'b1;
	 end
	else begin
	  	lock =1'b0;
	  	output_port = 1'b0;
	end
if (state == `DEBOUNCE) 
  output_port = 1'b1;
end		
endmodule