fir_top.tan.qmsg

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 187 1/20/2004 SJ Full Version " "Info: Version 4.0 Build 187 1/20/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 19 13:07:37 2004 " "Info: Processing started: Thu Feb 19 13:07:37 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off fir_top -c fir_top --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fir_top -c fir_top --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clock " "Info: Assuming node clock is an undefined clock" {  } { { "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" "" "" { Text "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/fir_top.vhd" 45 -1 0 } } { "c:/quartus4_0/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus4_0/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}