fir_top_inst.vhd

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· VHDL 代码 · 共 9 行

fir_top_inst : fir_top PORT MAP (
		clock	 => clock_sig,
		rst	 => rst_sig,
		data_in	 => data_in_sig,
		fir_result	 => fir_result_sig,
		rdy_to_ld	 => rdy_to_ld_sig,
		done	 => done_sig
	);