fir_top.tan.rpt

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· RPT 代码 · 共 196 行 · 第 1/5 页

; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg5 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[1]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg6 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[1]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg7 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[1]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg0 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg1 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg2 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg3 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg4 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg5 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg6 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg7 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[2]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg0 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg1 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg2 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg3 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg4 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg5 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg6 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg7 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[3]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg0 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg1 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg2 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg3 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg4 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg5 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg6 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg7 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[4]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg0 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg1 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg2 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg3 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg4 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg5 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg6 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~portb_address_reg7 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[5]                          ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.62 MHz ( period = 3.912 ns )                           ; fir_top_s