fir_top.tan.rpt

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· RPT 代码 · 共 196 行 · 第 1/5 页

+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clock           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                                                                                                                         ; To                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg12 ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg12 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg11 ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg11 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg10 ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg10 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg9  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg9  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg8  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg8  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg7  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg7  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg6  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg6  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg5  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg5  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg4  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg4  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg3  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg3  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg2  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg2  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg1  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg1  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_datain_reg0  ; fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|ram_block1a0~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg12 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg12 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg11 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg11 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg10 ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg10 ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg9  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg9  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg8  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg8  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg7  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg7  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg6  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg6  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg5  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg5  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg4  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg4  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg3  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg3  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg2  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg2  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg1  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg1  ; clock      ; clock    ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_datain_reg0  ; fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|ram_block1a0~porta_memory_reg0  ; clock      ; clock    ; None                        ; None                      ; None                    ;